Hi,
Thanks, for the reply. Geany picks up the file type ok, and filetypes.vhdl has a full list of key words.
What I meant by symbols was the symbols tab at the the right-hand side of the window. When editing a C file this list functions, variables etc. I'd like similar functionality for VHDL and Verilog.
Regards, Kelvin
Chow Loong Jin wrote:
Hi Kelvin, On Friday 20,November,2009 05:27 PM, Kelvin Gardiner wrote:
Hi,
I've been looking at Geany for editing VHDL / Verilog files. Overall it works well with the exception of picking up symbols in the code. VHDL variables are recognizing (is this a because variable var_name is used for another language?) but signals are not.
Did you make sure Geany's recognizing that file as a VHDL file? (Documents->Set Filetype->Programming Languages->VHDL source file) I haven't actually used Geany for VHDL files before though.
How does Geany recognize symbols, I can't find any config files (I may of missed them) so presumably it is done in the code. How hard would it be to add symbol recognition for VHDL / Verilog. If it is reasonably straight forward I don't mind try to do this.
I think the stuff's usually in /usr/share/geany, specifically /usr/share/geany/filetypes.vhdl. If you want to add more keywords, you could probably add them to the "keywords" line in that file. You'd probably want to copy it over to ~/.config/geany/filedefs first though, to prevent your changes from being overriden if/when you upgrade Geany.
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