Hi,
I've been looking at Geany for editing VHDL / Verilog files. Overall it works well with the exception of picking up symbols in the code. VHDL variables are recognizing (is this a because variable var_name is used for another language?) but signals are not.
How does Geany recognize symbols, I can't find any config files (I may of missed them) so presumably it is done in the code. How hard would it be to add symbol recognition for VHDL / Verilog. If it is reasonably straight forward I don't mind try to do this.
Regards, Kelvin Gardiner
Hi Kelvin, On Friday 20,November,2009 05:27 PM, Kelvin Gardiner wrote:
Hi,
I've been looking at Geany for editing VHDL / Verilog files. Overall it works well with the exception of picking up symbols in the code. VHDL variables are recognizing (is this a because variable var_name is used for another language?) but signals are not.
Did you make sure Geany's recognizing that file as a VHDL file? (Documents->Set Filetype->Programming Languages->VHDL source file) I haven't actually used Geany for VHDL files before though.
How does Geany recognize symbols, I can't find any config files (I may of missed them) so presumably it is done in the code. How hard would it be to add symbol recognition for VHDL / Verilog. If it is reasonably straight forward I don't mind try to do this.
I think the stuff's usually in /usr/share/geany, specifically /usr/share/geany/filetypes.vhdl. If you want to add more keywords, you could probably add them to the "keywords" line in that file. You'd probably want to copy it over to ~/.config/geany/filedefs first though, to prevent your changes from being overriden if/when you upgrade Geany.
Hi,
Thanks, for the reply. Geany picks up the file type ok, and filetypes.vhdl has a full list of key words.
What I meant by symbols was the symbols tab at the the right-hand side of the window. When editing a C file this list functions, variables etc. I'd like similar functionality for VHDL and Verilog.
Regards, Kelvin
Chow Loong Jin wrote:
Hi Kelvin, On Friday 20,November,2009 05:27 PM, Kelvin Gardiner wrote:
Hi,
I've been looking at Geany for editing VHDL / Verilog files. Overall it works well with the exception of picking up symbols in the code. VHDL variables are recognizing (is this a because variable var_name is used for another language?) but signals are not.
Did you make sure Geany's recognizing that file as a VHDL file? (Documents->Set Filetype->Programming Languages->VHDL source file) I haven't actually used Geany for VHDL files before though.
How does Geany recognize symbols, I can't find any config files (I may of missed them) so presumably it is done in the code. How hard would it be to add symbol recognition for VHDL / Verilog. If it is reasonably straight forward I don't mind try to do this.
I think the stuff's usually in /usr/share/geany, specifically /usr/share/geany/filetypes.vhdl. If you want to add more keywords, you could probably add them to the "keywords" line in that file. You'd probably want to copy it over to ~/.config/geany/filedefs first though, to prevent your changes from being overriden if/when you upgrade Geany.
Geany-devel mailing list Geany-devel@uvena.de http://lists.uvena.de/cgi-bin/mailman/listinfo/geany-devel
On Fri, 20 Nov 2009 11:45:16 +0000 Kelvin Gardiner kelvin@mbmn.net wrote:
What I meant by symbols was the symbols tab at the the right-hand side of the window. When editing a C file this list functions, variables etc. I'd like similar functionality for VHDL and Verilog.
If you provide a sample file I can try to improve the symbols parsed.
I think probably the problem is the tagmanager/vhdl.c parser hasn't been updated to work with tagmanager tag types (VhdlKinds).
Regards, Nick
I've attached a simple counter testbench. I've compiled the current code from svn and get the same issue. The only other tag listed in the VHDL tag file that works is function. Is the correct set of tags been called?
Thanks, Kelvin
Nick Treleaven wrote:
On Fri, 20 Nov 2009 11:45:16 +0000 Kelvin Gardiner kelvin@mbmn.net wrote:
What I meant by symbols was the symbols tab at the the right-hand side of the window. When editing a C file this list functions, variables etc. I'd like similar functionality for VHDL and Verilog.
If you provide a sample file I can try to improve the symbols parsed.
I think probably the problem is the tagmanager/vhdl.c parser hasn't been updated to work with tagmanager tag types (VhdlKinds).
Regards, Nick _______________________________________________ Geany-devel mailing list Geany-devel@uvena.de http://lists.uvena.de/cgi-bin/mailman/listinfo/geany-devel
On Fri, 20 Nov 2009 13:41:17 +0000 Kelvin Gardiner kelvin@mbmn.net wrote:
I've attached a simple counter testbench. I've compiled the current code
Thanks.
from svn and get the same issue. The only other tag listed in the VHDL tag file that works is function. Is the correct set of tags been called?
I made a small change to get signals in the symbol list. You might like to look at the commit and the HACKING file and make a patch to get other tag types shown for VHDL:
http://geany.svn.sourceforge.net/viewvc/geany?view=rev&revision=4446
Also, it's worth saying that the CTags VHDL parser has been updated quite a bit but this has made it 3 times bigger. Not sure whether we want to upgrade to that.
Nick Treleaven wrote:
On Fri, 20 Nov 2009 11:45:16 +0000 Kelvin Gardiner kelvin@mbmn.net wrote:
What I meant by symbols was the symbols tab at the the right-hand side of the window. When editing a C file this list functions, variables etc. I'd like similar functionality for VHDL and Verilog.
If you provide a sample file I can try to improve the symbols parsed.
I think probably the problem is the tagmanager/vhdl.c parser hasn't been updated to work with tagmanager tag types (VhdlKinds).
Regards, Nick
Hi,
Thanks for the patch. I've just had chance to give it a try. I'll have a look at fixing the other VHDL tags, and send a patch when done.
Regards, Kelvin
Nick Treleaven wrote:
On Fri, 20 Nov 2009 13:41:17 +0000 Kelvin Gardiner kelvin@mbmn.net wrote:
I've attached a simple counter testbench. I've compiled the current code
Thanks.
from svn and get the same issue. The only other tag listed in the VHDL tag file that works is function. Is the correct set of tags been called?
I made a small change to get signals in the symbol list. You might like to look at the commit and the HACKING file and make a patch to get other tag types shown for VHDL:
http://geany.svn.sourceforge.net/viewvc/geany?view=rev&revision=4446
Also, it's worth saying that the CTags VHDL parser has been updated quite a bit but this has made it 3 times bigger. Not sure whether we want to upgrade to that.
Nick Treleaven wrote:
On Fri, 20 Nov 2009 11:45:16 +0000 Kelvin Gardiner kelvin@mbmn.net wrote:
What I meant by symbols was the symbols tab at the the right-hand side of the window. When editing a C file this list functions, variables etc. I'd like similar functionality for VHDL and Verilog.
If you provide a sample file I can try to improve the symbols parsed.
I think probably the problem is the tagmanager/vhdl.c parser hasn't been updated to work with tagmanager tag types (VhdlKinds).
Regards, Nick _______________________________________________ Geany-devel mailing list Geany-devel@uvena.de http://lists.uvena.de/cgi-bin/mailman/listinfo/geany-devel
Hi,
I've fixed the VHDL symbols, two patches are attached for src/symbols.c and tagmanager/vhdl.c.
The changes are:
Added support of Alias symbol in symbols.c Renamed / added symbols groups and added icons for displayed groups in symbols.c Correct symbol types in vhdl.c
In some cases several symbols are in the same group. For example VHDL variables, signals and constants are similar to variables in other programming languages, so all this types are grouped as variables. I've done this to avoid introducing VHDL specific symbol types.
I tried creating a tags file for auto-completing functions in standard IEEE VHDL packages (similar to having gtk tags). I've done this by adding vhdl.tags in to /usr/share/geany but this doesn't work. I copied c99.tags to vhdl.tags and that didn't work either so presumably I need to add something else somewhere to get this working. What do I need to do?
I'd like to create symbols for Verilog as well. If I copy vhdl.c and change it as needed and modify the symbols.c to pickup Verilog files. Will these symbols get picked up or do I need to get geany to recognise Verilog files. Also, how to get geany to do syntax highlighting for Verilog.
Regards, Kelvin
Kelvin Gardiner wrote:
Hi,
Thanks for the patch. I've just had chance to give it a try. I'll have a look at fixing the other VHDL tags, and send a patch when done.
Regards, Kelvin
Nick Treleaven wrote:
On Fri, 20 Nov 2009 13:41:17 +0000 Kelvin Gardiner kelvin@mbmn.net wrote:
I've attached a simple counter testbench. I've compiled the current code
Thanks.
from svn and get the same issue. The only other tag listed in the VHDL tag file that works is function. Is the correct set of tags been called?
I made a small change to get signals in the symbol list. You might like to look at the commit and the HACKING file and make a patch to get other tag types shown for VHDL:
http://geany.svn.sourceforge.net/viewvc/geany?view=rev&revision=4446
Also, it's worth saying that the CTags VHDL parser has been updated quite a bit but this has made it 3 times bigger. Not sure whether we want to upgrade to that.
Nick Treleaven wrote:
On Fri, 20 Nov 2009 11:45:16 +0000 Kelvin Gardiner kelvin@mbmn.net wrote:
What I meant by symbols was the symbols tab at the the right-hand side of the window. When editing a C file this list functions, variables etc. I'd like similar functionality for VHDL and Verilog.
If you provide a sample file I can try to improve the symbols parsed.
I think probably the problem is the tagmanager/vhdl.c parser hasn't been updated to work with tagmanager tag types (VhdlKinds).
Regards, Nick _______________________________________________ Geany-devel mailing list Geany-devel@uvena.de http://lists.uvena.de/cgi-bin/mailman/listinfo/geany-devel
Geany-devel mailing list Geany-devel@uvena.de http://lists.uvena.de/cgi-bin/mailman/listinfo/geany-devel
On Thu, 26 Nov 2009 11:03:31 +0000 Kelvin Gardiner kelvin@mbmn.net wrote:
I've fixed the VHDL symbols, two patches are attached for src/symbols.c and tagmanager/vhdl.c.
Thanks, applied.
I tried creating a tags file for auto-completing functions in standard IEEE VHDL packages (similar to having gtk tags). I've done this by adding vhdl.tags in to /usr/share/geany but this doesn't work. I copied c99.tags to vhdl.tags and that didn't work either so presumably I need to add something else somewhere to get this working. What do I need to do?
Check the manual - it should be called something like std.vhdl.tags and placed in /usr/share/geany/tags or ~/.config/geany/tags.
I'd like to create symbols for Verilog as well. If I copy vhdl.c and change it as needed and modify the symbols.c to pickup Verilog files. Will these symbols get picked up or do I need to get geany to recognise Verilog files. Also, how to get geany to do syntax highlighting for Verilog.
It sounds like you want a new filetype for Verilog as it seems this is quite different from VHDL. See the HACKING file for how to add a filetype. There is a Verilog tag parser in the ctags project you could adapt and a lexer for highlighting in the Scintilla project src directory.
Regards, Nick
Hi,
I've attached a number of patches and new files to add Verilog syntax highlighting and symbols. I've taken the Verilog lexer directly from Scintilla.
Regards, Kelvin
Nick Treleaven wrote:
On Thu, 26 Nov 2009 11:03:31 +0000 Kelvin Gardiner kelvin@mbmn.net wrote:
I've fixed the VHDL symbols, two patches are attached for src/symbols.c and tagmanager/vhdl.c.
Thanks, applied.
I tried creating a tags file for auto-completing functions in standard IEEE VHDL packages (similar to having gtk tags). I've done this by adding vhdl.tags in to /usr/share/geany but this doesn't work. I copied c99.tags to vhdl.tags and that didn't work either so presumably I need to add something else somewhere to get this working. What do I need to do?
Check the manual - it should be called something like std.vhdl.tags and placed in /usr/share/geany/tags or ~/.config/geany/tags.
I'd like to create symbols for Verilog as well. If I copy vhdl.c and change it as needed and modify the symbols.c to pickup Verilog files. Will these symbols get picked up or do I need to get geany to recognise Verilog files. Also, how to get geany to do syntax highlighting for Verilog.
It sounds like you want a new filetype for Verilog as it seems this is quite different from VHDL. See the HACKING file for how to add a filetype. There is a Verilog tag parser in the ctags project you could adapt and a lexer for highlighting in the Scintilla project src directory.
Regards, Nick _______________________________________________ Geany-devel mailing list Geany-devel@uvena.de http://lists.uvena.de/cgi-bin/mailman/listinfo/geany-devel
On Fri, 27 Nov 2009 20:02:45 +0000 Kelvin Gardiner kelvin@mbmn.net wrote:
Hi,
I've attached a number of patches and new files to add Verilog syntax highlighting and symbols. I've taken the Verilog lexer directly from Scintilla.
Thanks for the patch & sorry for the slow response. It's now applied in SVN, with some changes:
Adjusted some styleset_verilog_init allocations that were too big. Removed the commented VHDL symbols.c lines (not sure what they were for). Added a get.h include to verilog.c to fix build.
BTW You might like to use the 'svn diff >patch.diff' command another time as it's probably easier than diffing each file manually ;-)
Regards, Nick
On Mon, 7 Dec 2009 17:57:18 +0000 Nick Treleaven nick.treleaven@btinternet.com wrote:
I've attached a number of patches and new files to add Verilog syntax highlighting and symbols. I've taken the Verilog lexer directly from Scintilla.
Thanks for the patch & sorry for the slow response. It's now applied in SVN, with some changes:
Also just committed: Fix using common style colours for Verilog.
We like the default style colours to be reasonably consistent across filetypes.
Regards, Nick