Branch: refs/heads/master Author: Jiří Techet techet@gmail.com Committer: GitHub noreply@github.com Date: Wed, 20 Nov 2024 13:45:41 UTC Commit: f998f789fa0424fc928ba86a5be7b7ab69a1ef9c https://github.com/geany/geany/commit/f998f789fa0424fc928ba86a5be7b7ab69a1ef...
Log Message: ----------- Merge pull request #4039 from cousteaulecommandant/sv
Add support for SystemVerilog
Modified Paths: -------------- data/Makefile.am data/filedefs/filetypes.SystemVerilog.conf data/filetype_extensions.conf src/tagmanager/tm_parser.c src/tagmanager/tm_parser.h src/tagmanager/tm_parsers.h tests/ctags/Makefile.am tests/ctags/bug1111214-j-chan.v.tags tests/ctags/bug1111214.v.tags tests/ctags/bug1743330.v.tags tests/ctags/bug2747828.v.tags tests/ctags/bug960316.v.tags tests/ctags/bug961001.v.tags tests/ctags/oop.sv tests/ctags/oop.sv.tags tests/ctags/state_machine.v.tags tests/ctags/sysverilog.sv tests/ctags/sysverilog.sv.tags tests/ctags/traffic_signal.v.tags tests/meson.build
Modified: data/Makefile.am 1 lines changed, 1 insertions(+), 0 deletions(-) =================================================================== @@ -77,6 +77,7 @@ filetypes_dist = \ filedefs/filetypes.smalltalk \ filedefs/filetypes.sql \ filedefs/filetypes.Swift.conf \ + filedefs/filetypes.SystemVerilog.conf \ filedefs/filetypes.TypeScript.conf \ filedefs/filetypes.tcl \ filedefs/filetypes.txt2tags \
Modified: data/filedefs/filetypes.SystemVerilog.conf 45 lines changed, 45 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,45 @@ +# For complete documentation of this file, please see Geany's main documentation +[styling=Verilog] + +[keywords] +# all items must be in one line +word=accept_on alias always always_comb always_ff always_latch and assert assign assume automatic before begin bind bins binsof break buf bufif0 bufif1 case casex casez cell checker class clocking cmos config const constraint context continue cover covergroup coverpoint cross deassign default defparam design disable dist do edge else end endcase endchecker endclass endclocking endconfig endfunction endgenerate endgroup endinterface endmodule endpackage endprimitive endprogram endproperty endsequence endspecify endtable endtask enum eventually expect export extends extern final first_match for force foreach forever fork forkjoin function generate global if iff ifnone ignore_bins illegal_bins implements implies import incdir include initial inside instance interface intersect join join_any join_none let liblist library local macromodule matches modport module nand negedge nettype new nexttime nmos nor noshowcancelled not notif0 notif1 null or package packed pmos posedge primitive prio rity program property protected pulldown pullup pulsestyle_ondetect pulsestyle_onevent pure rand randc randcase randsequence rcmos reject_on release repeat restrict return rnmos rpmos rtran rtranif0 rtranif1 s_always s_eventually s_nexttime s_until s_until_with sequence showcancelled soft solve specify static strong struct super sync_accept_on sync_reject_on table tagged task this throughout timeprecision timeunit tran tranif0 tranif1 typedef union unique unique0 until until_with untyped use virtual wait wait_order weak while wildcard with within xnor xor +word2=$acos $acosh $asin $asinh $assertcontrol $assertfailoff $assertfailon $assertkill $assertnonvacuouson $assertoff $asserton $assertpassoff $assertpasson $assertvacuousoff $async$and$array $async$and$plane $async$nand$array $async$nand$plane $async$nor$array $async$nor$plane $async$or$array $async$or$plane $atan $atan2 $atanh $bits $bitstoreal $bitstoshortreal $cast $ceil $changed $changed_gclk $changing_gclk $clog2 $cos $cosh $countbits $countones $coverage_control $coverage_get $coverage_get_max $coverage_merge $coverage_save $dimensions $display $displayb $displayh $displayo $dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform $dumpall $dumpfile $dumpflush $dumplimit $dumpoff $dumpon $dumpports $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff $dumpportson $dumpvars $error $exit $exp $falling_gclk $fatal $fclose $fdisplay $fdisplayb $fdisplayh $fdisplayo $fell $fell_gclk $feof $ferror $fflush $fgetc $fgets $finish $floor $ fmonitor $fmonitorb $fmonitorh $fmonitoro $fopen $fread $fscanf $fseek $fstrobe $fstrobeb $fstrobeh $fstrobeo $ftell $future_gclk $fwrite $fwriteb $fwriteh $fwriteo $get_coverage $high $hypot $increment $info $isunbounded $isunknown $itor $left $ln $load_coverage_db $log10 $low $monitor $monitorb $monitorh $monitoro $monitoroff $monitoron $onehot $onehot0 $past $past_gclk $pow $printtimescale $q_add $q_exam $q_full $q_initialize $q_remove $random $readmemb $readmemh $realtime $realtobits $rewind $right $rising_gclk $rose $rose_gclk $rtoi $sampled $set_coverage_db_name $sformat $sformatf $shortrealtobits $signed $sin $sinh $size $sqrt $sscanf $stable $stable_gclk $steady_gclk $stime $stop $strobe $strobeb $strobeh $strobeo $swrite $swriteb $swriteh $swriteo $sync$and$array $sync$and$plane $sync$nand$array $sync$nand$plane $sync$nor$array $sync$nor$plane $sync$or$array $sync$or$plane $system $tan $tanh $test$plusargs $time $timeformat $typename $ungetc $unpacked_dimensions $unsigned $ value$plusargs $warning $write $writeb $writeh $writememb $writememh $writeo +word3=bit byte chandle event genvar highz0 highz1 inout input int integer interconnect large localparam logic longint medium output parameter pull0 pull1 real realtime ref reg scalared shortint shortreal signed small specparam string strong0 strong1 supply0 supply1 time tri tri0 tri1 triand trior trireg type unsigned uwire var vectored void wand weak0 weak1 wire wor +docComment= + +[settings] +lexer_filetype=Verilog +tag_parser=SystemVerilog + +# default extension used when saving files +extension=sv + +# MIME type +mime_type=text/x-systemverilog + +# these characters define word boundaries when making selections and searching +# using word matching options +#wordchars=_$abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789 + +# single comments, like # in this file +comment_single=// +# multiline comments +comment_open=/* +comment_close=*/ + +# set to false if a comment character/string should start at column 0 of a line, true uses any +# indentation of the line, e.g. setting to true causes the following on pressing CTRL+d +# #command_example(); +# setting to false would generate this +# # command_example(); +# This setting works only for single line comments +comment_use_indent=true + +# context action command (please see Geany's main documentation for details) +context_action_cmd= + +[indentation] +#width=4 +# 0 is spaces, 1 is tabs, 2 is tab & spaces +#type=1
Modified: data/filetype_extensions.conf 5 lines changed, 3 insertions(+), 2 deletions(-) =================================================================== @@ -76,11 +76,12 @@ Sh=*.sh;configure;configure.in;configure.in.in;configure.ac;*.ksh;*.mksh;*.zsh;* Smalltalk=*.st; SQL=*.sql; Swift=*.swift; +SystemVerilog=*.sv;*.svh; Tcl=*.tcl;*.tk;*.wish;*.exp; Txt2tags=*.t2t; TypeScript=*.ts;*.cts;*.mts;*.tsx; Vala=*.vala;*.vapi; -Verilog=*.v; +Verilog=*.v;*.vh; VHDL=*.vhd;*.vhdl; XML=*.xml;*.sgml;*.xsl;*.xslt;*.xsd;*.xhtml;*.xul;*.dtd;*.xtpl;*.mml;*.mathml; YAML=*.yaml;*.yml; @@ -90,7 +91,7 @@ None=*;
# Note: restarting is required after editing groups [Groups] -Programming=Arduino;Clojure;CUDA;Cython;Genie;Groovy;Kotlin;Scala;Swift; +Programming=Arduino;Clojure;CUDA;Cython;Genie;Groovy;Kotlin;Scala;Swift;SystemVerilog; Script=Dockerfile;Graphviz;TypeScript;Meson; Markup= Misc=JSON;
Modified: src/tagmanager/tm_parser.c 69 lines changed, 55 insertions(+), 14 deletions(-) =================================================================== @@ -768,26 +768,65 @@ static TMParserMapEntry map_ABC[] = { }; #define group_ABC group_REST
+#define COMMON_VERILOG \ + {'c', tm_tag_field_t}, /* constant */ \ + {'d', tm_tag_macro_t}, /* define */ \ + {'e', tm_tag_variable_t}, /* event */ \ + {'f', tm_tag_function_t}, /* function */ \ + {'m', tm_tag_prototype_t}, /* module */ \ + {'n', tm_tag_variable_t}, /* net */ \ + {'p', tm_tag_externvar_t}, /* port */ \ + {'r', tm_tag_variable_t}, /* register */ \ + {'t', tm_tag_function_t}, /* task */ \ + {'b', tm_tag_namespace_t}, /* block */ \ + {'i', tm_tag_enumerator_t}, /* instance */ + static TMParserMapEntry map_VERILOG[] = { - {'c', tm_tag_variable_t}, // constant - {'d', tm_tag_variable_t}, // define - {'e', tm_tag_typedef_t}, // event - {'f', tm_tag_function_t}, // function - {'m', tm_tag_class_t}, // module - {'n', tm_tag_variable_t}, // net - {'p', tm_tag_variable_t}, // port - {'r', tm_tag_variable_t}, // register - {'t', tm_tag_function_t}, // task - {'b', tm_tag_undef_t}, // block - {'i', tm_tag_undef_t}, // instance + COMMON_VERILOG }; static TMParserMapGroup group_VERILOG[] = { - {N_("Events"), TM_ICON_MACRO, tm_tag_typedef_t}, - {N_("Modules"), TM_ICON_CLASS, tm_tag_class_t}, + /* Verilog and SystemVerilog */ + {N_("Modules"), TM_ICON_CLASS, tm_tag_prototype_t}, + {N_("Instances"), TM_ICON_OTHER, tm_tag_enumerator_t}, + {N_("Blocks"), TM_ICON_NAMESPACE, tm_tag_namespace_t}, {N_("Functions / Tasks"), TM_ICON_METHOD, tm_tag_function_t}, - {N_("Variables"), TM_ICON_VAR, tm_tag_variable_t}, + {N_("Macros"), TM_ICON_MACRO, tm_tag_macro_t}, + {N_("Parameters / Constants"), TM_ICON_MACRO, tm_tag_field_t}, + {N_("Ports"), TM_ICON_MEMBER, tm_tag_externvar_t}, + {N_("Signals"), TM_ICON_VAR, tm_tag_variable_t}, + /* SystemVerilog only */ + {N_("Classes"), TM_ICON_STRUCT, tm_tag_class_t}, + {N_("Interfaces"), TM_ICON_STRUCT, tm_tag_interface_t | tm_tag_union_t}, + {N_("Package"), TM_ICON_NAMESPACE, tm_tag_package_t}, + {N_("Members"), TM_ICON_MEMBER, tm_tag_member_t}, + {N_("Structs"), TM_ICON_STRUCT, tm_tag_struct_t}, + {N_("Typedefs / Enums"), TM_ICON_STRUCT, tm_tag_typedef_t | tm_tag_enum_t}, };
+static TMParserMapEntry map_SYSVERILOG[] = { + COMMON_VERILOG + {'A', tm_tag_undef_t}, // assert + {'C', tm_tag_class_t}, // class + {'V', tm_tag_undef_t}, // covergroup + {'E', tm_tag_enum_t}, // enum + {'I', tm_tag_interface_t}, // interface + {'M', tm_tag_union_t}, // modport + {'K', tm_tag_package_t}, // package + {'P', tm_tag_prototype_t}, // program + {'Q', tm_tag_function_t}, // prototype + {'R', tm_tag_undef_t}, // property + {'S', tm_tag_struct_t}, // struct + {'T', tm_tag_typedef_t}, // typedef + {'H', tm_tag_undef_t}, // checker + {'L', tm_tag_undef_t}, // clocking + {'q', tm_tag_undef_t}, // sequence + {'w', tm_tag_member_t}, // member + {'l', tm_tag_class_t}, // ifclass + {'O', tm_tag_undef_t}, // constraint + {'N', tm_tag_typedef_t}, // nettype +}; +#define group_SYSVERILOG group_VERILOG + static TMParserMapEntry map_R[] = { {'f', tm_tag_function_t}, // function {'l', tm_tag_other_t}, // library @@ -1280,6 +1319,7 @@ static TMParserMap parser_map[] = { MAP_ENTRY(LDSCRIPT), MAP_ENTRY(FORTH), MAP_ENTRY(MESON), + MAP_ENTRY(SYSVERILOG), }; /* make sure the parser map is consistent and complete */ G_STATIC_ASSERT(G_N_ELEMENTS(parser_map) == TM_PARSER_COUNT); @@ -1811,6 +1851,7 @@ gboolean tm_parser_has_full_scope(TMParserType lang) case TM_PARSER_VALA: case TM_PARSER_VHDL: case TM_PARSER_VERILOG: + case TM_PARSER_SYSVERILOG: case TM_PARSER_ZEPHIR: case TM_PARSER_AUTOIT: return TRUE;
Modified: src/tagmanager/tm_parser.h 1 lines changed, 1 insertions(+), 0 deletions(-) =================================================================== @@ -144,6 +144,7 @@ enum TM_PARSER_LDSCRIPT, TM_PARSER_FORTH, TM_PARSER_MESON, + TM_PARSER_SYSVERILOG, TM_PARSER_COUNT };
Modified: src/tagmanager/tm_parsers.h 3 lines changed, 2 insertions(+), 1 deletions(-) =================================================================== @@ -78,6 +78,7 @@ OcamlParser, \ LdScriptParser, \ ForthParser, \ - MesonParser + MesonParser, \ + SystemVerilogParser
#endif
Modified: tests/ctags/Makefile.am 2 lines changed, 2 insertions(+), 0 deletions(-) =================================================================== @@ -263,6 +263,7 @@ test_sources = \ objectivec_interface.mm \ objectivec_property.mm \ objectivec_protocol.mm \ + oop.sv \ Package.pm \ php5_5_class_kw.php \ parenthesis-rvalue.js \ @@ -341,6 +342,7 @@ test_sources = \ strings.php \ strings.rb \ structure.f \ + sysverilog.sv \ tabindent.py \ test.erl \ test.go \
Modified: tests/ctags/bug1111214-j-chan.v.tags 12 lines changed, 6 insertions(+), 6 deletions(-) =================================================================== @@ -1,6 +1,6 @@ -insig�16384�top�0 -variable: top :: insig -outsig�16384�top�0 -variable: top :: outsig -top�1�0 -class: top +insig�32768�top�0 +externvar: top :: insig +outsig�32768�top�0 +externvar: top :: outsig +top�1024�0 +prototype: top
Modified: tests/ctags/bug1111214.v.tags 4 lines changed, 2 insertions(+), 2 deletions(-) =================================================================== @@ -1,2 +1,2 @@ -wahoo�1�0 -class: wahoo +wahoo�1024�0 +prototype: wahoo
Modified: tests/ctags/bug1743330.v.tags 4 lines changed, 2 insertions(+), 2 deletions(-) =================================================================== @@ -1,2 +1,2 @@ -dummy�1�0 -class: dummy +dummy�1024�0 +prototype: dummy
Modified: tests/ctags/bug2747828.v.tags 4 lines changed, 2 insertions(+), 2 deletions(-) =================================================================== @@ -1,2 +1,2 @@ -ramaddr_0�16384�0 -variable: ramaddr_0 +ramaddr_0�8�0 +field: ramaddr_0
Modified: tests/ctags/bug960316.v.tags 8 lines changed, 4 insertions(+), 4 deletions(-) =================================================================== @@ -1,11 +1,11 @@ -fail_define_2�16384�0 -variable: fail_define_2 +fail_define_2�65536�0 +macro: fail_define_2 fail_func_2�16�0 function: fail_func_2 fail_task_2�16�0 function: fail_task_2 -pass_define_1�16384�0 -variable: pass_define_1 +pass_define_1�65536�0 +macro: pass_define_1 pass_func_1�16�0 function: pass_func_1 pass_task_1�16�0
Modified: tests/ctags/bug961001.v.tags 32 lines changed, 16 insertions(+), 16 deletions(-) =================================================================== @@ -1,16 +1,16 @@ -GUESTA�16384�0 -variable: GUESTA -GUESTB�16384�0 -variable: GUESTB -GUESTC�16384�0 -variable: GUESTC -GUESTD�16384�0 -variable: GUESTD -HOSTA�16384�0 -variable: HOSTA -HOSTB�16384�0 -variable: HOSTB -HOSTC�16384�0 -variable: HOSTC -HOSTD�16384�0 -variable: HOSTD +GUESTA�65536�0 +macro: GUESTA +GUESTB�65536�0 +macro: GUESTB +GUESTC�65536�0 +macro: GUESTC +GUESTD�65536�0 +macro: GUESTD +HOSTA�65536�0 +macro: HOSTA +HOSTB�65536�0 +macro: HOSTB +HOSTC�65536�0 +macro: HOSTC +HOSTD�65536�0 +macro: HOSTD
Modified: tests/ctags/oop.sv 145 lines changed, 145 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,145 @@ +/* Tests the following SystemVerilog ctags: + * - [x] constant + * - [x] define + * - [ ] event + * - [x] function + * - [ ] module + * - [ ] net + * - [ ] port + * - [x] register + * - [x] task + * - [ ] block + * - [ ] instance + * - [x] class + * - [x] enum + * - [x] interface + * - [x] modport + * - [x] package + * - [ ] program + * - [x] prototype + * - [x] struct + * - [x] typedef + * - [z] member + * - [x] ifclass + * - [x] nettype + */ + +package oop; + +`define MACRO 1234 // NB: Shouldn't the ctag for this be outside of the package? (ctags bug?) + +/* Constants */ + +const int ANSWER_TO_LIFE = 42; +localparam real APPROX_PI = 3.14; + +/* Methods */ + +task display_int(int x); + $display("%0d", x); +endtask + +function automatic resolve_nettype(real driver[]); + resolve_nettype = 0.0; + foreach (driver[i]) + resolve_nettype += driver[i]; +endfunction + +/* Typedefs */ + +nettype real net_t with resolve_nettype; + +typedef struct packed { + logic [7:0] data; + logic parity; +} struct_t; + +typedef union packed { + logic [7:0] data; + logic [3:0] control; +} union_t; + +typedef enum { + red, + yellow, + green +} enum_t; + +/* Classes */ + +interface class ifclass #( + type T = logic +); + pure virtual function T get_value(); + pure virtual function void set_value(T x); +endclass : ifclass + +class a_class implements ifclass #(int); + + int value; + + virtual function int get_value(); + get_value = value; + endfunction + + virtual function void put_value(int x); + value = x; + endfunction + + task print_value(); + $display("value = %0d", value); + endtask + + function value_plus(int x); + value_plus = value + x; + endfunction + +endclass : a_class + +class other_class; + + struct packed { + byte s_a, s_b, s_c; + string s_str; + } s_member; + + union packed { + byte u_a; + int u_b; + } u_member; + + enum { ready, steady, go } e_member; + + struct_t st_member; + union_t ut_member; + enum_t et_member; + +endclass : other_class + +/*virtual*/ class vclass; // NB: ctags bug!! Declaring class as virtual inhibits detection of next element. + pure virtual function void do_something(); +endclass : vclass + +/* Interface (not related to "interface class") */ + +interface spi; + + logic sclk; + logic cs_n; + logic mosi; + logic miso; + + modport master (output sclk, cs_n, mosi, input miso); + modport slave (input sclk, cs_n, mosi, output miso); + + task enable_cs(); + cs_n <= 1'b0; + endtask + + task disable_cs(); + cs_n <= 1'b1; + endtask + +endinterface : spi + +endpackage : oop
Modified: tests/ctags/oop.sv.tags 118 lines changed, 118 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,118 @@ +ANSWER_TO_LIFE�16384�oop�0 +variable: oop :: ANSWER_TO_LIFE +APPROX_PI�8�oop�0 +field: oop :: APPROX_PI +MACRO�65536�oop�0 +macro: oop :: MACRO +T�8�oop.ifclass�0 +field: oop.ifclass :: T +a_class�1�oop�0 +class: oop :: a_class +control�64�oop.union_t�0 +member: oop.union_t :: control +cs_n�16384�oop.spi�0 +variable: oop.spi :: cs_n +data�64�oop.struct_t�0 +member: oop.struct_t :: data +data�64�oop.union_t�0 +member: oop.union_t :: data +disable_cs�16�oop.spi�0 +function: oop.spi :: disable_cs +display_int�16�oop�0 +function: oop :: display_int +do_something�16�oop.vclass�0 +function: oop.vclass :: do_something +driver�32768�oop.resolve_nettype�0 +externvar: oop.resolve_nettype :: driver +e_member�2�oop.other_class�0 +enum: oop.other_class :: e_member +enable_cs�16�oop.spi�0 +function: oop.spi :: enable_cs +enum_t�4096�oop�0 +typedef: oop :: enum_t +et_member�16384�oop.other_class�0 +variable: oop.other_class :: et_member +get_value�16�oop.a_class�0 +function: oop.a_class :: get_value +get_value�16�oop.ifclass�0 +function: oop.ifclass :: get_value +go�8�oop.other_class.e_member�0 +field: oop.other_class.e_member :: go +green�8�oop.enum_t�0 +field: oop.enum_t :: green +ifclass�1�oop�0 +class: oop :: ifclass +master�8192�oop.spi�0 +union: oop.spi :: master +miso�16384�oop.spi�0 +variable: oop.spi :: miso +mosi�16384�oop.spi�0 +variable: oop.spi :: mosi +net_t�4096�oop�0 +typedef: oop :: net_t +oop�512�0 +package: oop +other_class�1�oop�0 +class: oop :: other_class +parity�64�oop.struct_t�0 +member: oop.struct_t :: parity +print_value�16�oop.a_class�0 +function: oop.a_class :: print_value +put_value�16�oop.a_class�0 +function: oop.a_class :: put_value +ready�8�oop.other_class.e_member�0 +field: oop.other_class.e_member :: ready +red�8�oop.enum_t�0 +field: oop.enum_t :: red +resolve_nettype�16�oop�0 +function: oop :: resolve_nettype +s_a�64�oop.other_class.s_member�0 +member: oop.other_class.s_member :: s_a +s_b�64�oop.other_class.s_member�0 +member: oop.other_class.s_member :: s_b +s_c�64�oop.other_class.s_member�0 +member: oop.other_class.s_member :: s_c +s_member�2048�oop.other_class�0 +struct: oop.other_class :: s_member +s_str�64�oop.other_class.s_member�0 +member: oop.other_class.s_member :: s_str +sclk�16384�oop.spi�0 +variable: oop.spi :: sclk +set_value�16�oop.ifclass�0 +function: oop.ifclass :: set_value +slave�8192�oop.spi�0 +union: oop.spi :: slave +spi�32�oop�0 +interface: oop :: spi +st_member�16384�oop.other_class�0 +variable: oop.other_class :: st_member +steady�8�oop.other_class.e_member�0 +field: oop.other_class.e_member :: steady +struct_t�4096�oop�0 +typedef: oop :: struct_t +u_a�64�oop.other_class.u_member�0 +member: oop.other_class.u_member :: u_a +u_b�64�oop.other_class.u_member�0 +member: oop.other_class.u_member :: u_b +u_member�2048�oop.other_class�0 +struct: oop.other_class :: u_member +union_t�4096�oop�0 +typedef: oop :: union_t +ut_member�16384�oop.other_class�0 +variable: oop.other_class :: ut_member +value�16384�oop.a_class�0 +variable: oop.a_class :: value +value_plus�16�oop.a_class�0 +function: oop.a_class :: value_plus +vclass�1�oop�0 +class: oop :: vclass +x�32768�oop.a_class.put_value�0 +externvar: oop.a_class.put_value :: x +x�32768�oop.a_class.value_plus�0 +externvar: oop.a_class.value_plus :: x +x�32768�oop.display_int�0 +externvar: oop.display_int :: x +x�32768�oop.ifclass.set_value�0 +externvar: oop.ifclass.set_value :: x +yellow�8�oop.enum_t�0 +field: oop.enum_t :: yellow
Modified: tests/ctags/state_machine.v.tags 16 lines changed, 8 insertions(+), 8 deletions(-) =================================================================== @@ -1,11 +1,11 @@ -S0�16384�0 -variable: S0 -S1�16384�0 -variable: S1 -S2�16384�0 -variable: S2 -S3�16384�0 -variable: S3 +S0�8�0 +field: S0 +S1�8�0 +field: S1 +S2�8�0 +field: S2 +S3�8�0 +field: S3 next_state�16384�0 variable: next_state state�16384�0
Modified: tests/ctags/sysverilog.sv 192 lines changed, 192 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,192 @@ +/* Tests the following SystemVerilog ctags: + * - [x] constant + * - [x] define + * - [x] event + * - [x] function + * - [x] module + * - [x] net + * - [x] port + * - [x] register + * - [x] task + * - [x] block + * - [x] instance + * - [ ] class + * - [ ] enum + * - [ ] interface + * - [ ] modport + * - [ ] package + * - [x] program + * - [ ] prototype + * - [ ] struct + * - [ ] typedef + * - [ ] member + * - [ ] ifclass + * - [ ] nettype + */ + +`timescale 1ns/1ps +`default_nettype none + +`define DEFAULT_WIDTH 32 +`define BITS_TO_BYTES(x) ((x)/8) + +module a_module #( + parameter WIDTH = `DEFAULT_WIDTH, + localparam BYTES = `BITS_TO_BYTES(WIDTH) +) ( + input clk, reset, + input logic [WIDTH-1:0] data_in, + input logic valid, + input wire [BYTES-1:0] byte_en, + output wire [WIDTH-1:0] data_out +); + + wire be_filtered [BYTES-1:0]; + + genvar i; + generate + for (i = 0; i < BYTES; i++) begin : be_filtered_gen + logic x; + and and_gate ( // NB: this SHOULD be detected as an instance (ctags bug?) + x, + byte_en[i], + valid + ); + assign be_filtered[i] = x; + end + endgenerate + + wire [BYTES-1:0][7:0] data_in_bytes; + reg [BYTES-1:0][7:0] data_out_bytes; + + assign data_in_bytes = data_in; + assign data_out = data_out_bytes; + + always @(posedge clk, posedge reset) begin : main_block + if (reset) + data_out_bytes <= '0; + else begin + int i; + for (i = 0; i < BYTES; i++) + if (be_filtered[i]) + data_out_bytes[i] <= data_in_bytes[i]; + end + end + +endmodule : a_module + +program generate_signals #( + parameter NUM_UUT = 4, + parameter UUT_WIDTH = 64, + localparam UUT_BYTES = `BITS_TO_BYTES(UUT_WIDTH) +) ( + input logic clk, reset, + output logic [UUT_WIDTH-1:0] data_in, + output logic valid_uut [NUM_UUT-1:0], + output logic [UUT_BYTES-1:0] byte_en, + output event finished // NB: counts as "port", not "event" +); + + task write_byte( + byte byte_data, + int byte_index, + int uut_index + ); + begin + logic [UUT_BYTES-1:0][7:0] data_in_bytes; + data_in_bytes = '0; + data_in_bytes[byte_index] = byte_data; + data_in = data_in_bytes; + byte_en = UUT_BYTES'(1) << byte_index; + + valid_uut[uut_index] <= 1'b1; + @(posedge clk); + valid_uut[uut_index] <= 1'b0; + end + endtask + + initial begin + @(negedge reset); + @(posedge clk); + + write_byte(8'h12, 3, 0); + write_byte(8'h34, 2, 0); + write_byte(8'h56, 1, 0); + write_byte(8'h78, 0, 0); + + @(posedge clk); + + -> finished; + end + +endprogram : generate_signals + +module testbench; + + localparam NUM_UUT = 4; + localparam UUT_WIDTH = 64; + localparam UUT_BYTES = `BITS_TO_BYTES(UUT_WIDTH); + + logic clk = 1'b0, reset = 1'b0; + logic [UUT_WIDTH-1:0] data_in; + logic valid_uut [NUM_UUT-1:0]; + logic [UUT_BYTES-1:0] byte_en; + + generate + for (genvar j = 0; j < NUM_UUT; j++) begin : uut_gen + logic [UUT_WIDTH-1:0] data_out; + a_module #( // NB: this SHOULDN'T be detected as a module declaration (ctags bug) + .WIDTH (UUT_WIDTH) + ) uut ( // but this should be detected as an instance (ctags works) + .valid (valid_uut[j]), + .* + ); + end + endgenerate + + event trigger_success, trigger_failure, finished; + + function logic compare( + logic [UUT_BYTES-1:0][7:0] A, B, + logic [UUT_BYTES-1:0] mask + ); + begin + int i; + for (i = 0; i < UUT_BYTES; i++) + if (mask[i] && (A[i] != B[i])) begin + return 1'b0; + end + compare = 1'b1; // same as return 1'b1 + end + endfunction + + always begin : clk_gen + clk = ~clk; + #0.5; + end + + initial begin : reset_gen + reset = 1'b1; + #3.5; + reset = 1'b0; + end + + generate_signals #( + .NUM_UUT (NUM_UUT), + .UUT_WIDTH (UUT_WIDTH) + ) gen_signals ( + .* + ); + + initial begin + @finished; + + if (compare(uut_gen[0].data_out, 64'h 00000000_12_34_56_78, 8'b 0000_1111)) + $display("Comparison succeeded."); + else + $display("Comparison failed!"); + + $finish; + end + +endmodule : testbench
Modified: tests/ctags/sysverilog.sv.tags 118 lines changed, 118 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,118 @@ +A�32768�testbench.compare�0 +externvar: testbench.compare :: A +B�32768�testbench.compare�0 +externvar: testbench.compare :: B +BITS_TO_BYTES�65536�0 +macro: BITS_TO_BYTES +BYTES�8�a_module�0 +field: a_module :: BYTES +DEFAULT_WIDTH�65536�0 +macro: DEFAULT_WIDTH +NUM_UUT�8�generate_signals�0 +field: generate_signals :: NUM_UUT +NUM_UUT�8�testbench�0 +field: testbench :: NUM_UUT +UUT_BYTES�8�generate_signals�0 +field: generate_signals :: UUT_BYTES +UUT_BYTES�8�testbench�0 +field: testbench :: UUT_BYTES +UUT_WIDTH�8�generate_signals�0 +field: generate_signals :: UUT_WIDTH +UUT_WIDTH�8�testbench�0 +field: testbench :: UUT_WIDTH +WIDTH�8�a_module�0 +field: a_module :: WIDTH +a_module�1024�0 +prototype: a_module +a_module�1024�testbench.uut_gen�0 +prototype: testbench.uut_gen :: a_module +be_filtered�16384�a_module�0 +variable: a_module :: be_filtered +be_filtered_gen�256�a_module�0 +namespace: a_module :: be_filtered_gen +byte_data�32768�generate_signals.write_byte�0 +externvar: generate_signals.write_byte :: byte_data +byte_en�16384�testbench�0 +variable: testbench :: byte_en +byte_en�32768�a_module�0 +externvar: a_module :: byte_en +byte_en�32768�generate_signals�0 +externvar: generate_signals :: byte_en +byte_index�32768�generate_signals.write_byte�0 +externvar: generate_signals.write_byte :: byte_index +clk�16384�testbench�0 +variable: testbench :: clk +clk�32768�a_module�0 +externvar: a_module :: clk +clk�32768�generate_signals�0 +externvar: generate_signals :: clk +clk_gen�256�testbench�0 +namespace: testbench :: clk_gen +compare�16�testbench�0 +function: testbench :: compare +data_in�16384�testbench�0 +variable: testbench :: data_in +data_in�32768�a_module�0 +externvar: a_module :: data_in +data_in�32768�generate_signals�0 +externvar: generate_signals :: data_in +data_in_bytes�16384�a_module�0 +variable: a_module :: data_in_bytes +data_in_bytes�16384�generate_signals.write_byte�0 +variable: generate_signals.write_byte :: data_in_bytes +data_out�16384�testbench.uut_gen�0 +variable: testbench.uut_gen :: data_out +data_out�32768�a_module�0 +externvar: a_module :: data_out +data_out_bytes�16384�a_module�0 +variable: a_module :: data_out_bytes +finished�16384�testbench�0 +variable: testbench :: finished +finished�32768�generate_signals�0 +externvar: generate_signals :: finished +gen_signals�4�testbench�0�generate_signals +enumerator: generate_signals testbench :: gen_signals +generate_signals�1024�0 +prototype: generate_signals +generate_signals�1024�testbench�0 +prototype: testbench :: generate_signals +i�16384�a_module�0 +variable: a_module :: i +i�16384�a_module.main_block�0 +variable: a_module.main_block :: i +i�16384�testbench.compare�0 +variable: testbench.compare :: i +main_block�256�a_module�0 +namespace: a_module :: main_block +mask�32768�testbench.compare�0 +externvar: testbench.compare :: mask +reset�16384�testbench�0 +variable: testbench :: reset +reset�32768�a_module�0 +externvar: a_module :: reset +reset�32768�generate_signals�0 +externvar: generate_signals :: reset +reset_gen�256�testbench�0 +namespace: testbench :: reset_gen +testbench�1024�0 +prototype: testbench +trigger_failure�16384�testbench�0 +variable: testbench :: trigger_failure +trigger_success�16384�testbench�0 +variable: testbench :: trigger_success +uut�4�testbench.uut_gen�0�a_module +enumerator: a_module testbench.uut_gen :: uut +uut_gen�256�testbench�0 +namespace: testbench :: uut_gen +uut_index�32768�generate_signals.write_byte�0 +externvar: generate_signals.write_byte :: uut_index +valid�32768�a_module�0 +externvar: a_module :: valid +valid_uut�16384�testbench�0 +variable: testbench :: valid_uut +valid_uut�32768�generate_signals�0 +externvar: generate_signals :: valid_uut +write_byte�16�generate_signals�0 +function: generate_signals :: write_byte +x�16384�a_module.be_filtered_gen�0 +variable: a_module.be_filtered_gen :: x
Modified: tests/ctags/traffic_signal.v.tags 40 lines changed, 24 insertions(+), 16 deletions(-) =================================================================== @@ -1,26 +1,34 @@ +Init�256�traffic�0 +namespace: traffic :: Init amber�16384�traffic�0 variable: traffic :: amber -amber_tics�16384�traffic�0 -variable: traffic :: amber_tics +amber_tics�8�traffic�0 +field: traffic :: amber_tics clock�16384�traffic�0 variable: traffic :: clock -color�16384�traffic.light�0 -variable: traffic.light :: color +clock_wave�256�traffic�0 +namespace: traffic :: clock_wave +color�32768�traffic.light�0 +externvar: traffic.light :: color green�16384�traffic�0 variable: traffic :: green -green_tics�16384�traffic�0 -variable: traffic :: green_tics +green_tics�8�traffic�0 +field: traffic :: green_tics light�16�traffic�0 function: traffic :: light -off�16384�traffic�0 -variable: traffic :: off -on�16384�traffic�0 -variable: traffic :: on +main_process�256�traffic�0 +namespace: traffic :: main_process +off�8�traffic�0 +field: traffic :: off +on�8�traffic�0 +field: traffic :: on red�16384�traffic�0 variable: traffic :: red -red_tics�16384�traffic�0 -variable: traffic :: red_tics -tics�16384�traffic.light�0 -variable: traffic.light :: tics -traffic�1�0 -class: traffic +red_tics�8�traffic�0 +field: traffic :: red_tics +stop_at�256�traffic�0 +namespace: traffic :: stop_at +tics�32768�traffic.light�0 +externvar: traffic.light :: tics +traffic�1024�0 +prototype: traffic
Modified: tests/meson.build 2 lines changed, 2 insertions(+), 0 deletions(-) =================================================================== @@ -260,6 +260,7 @@ ctags_tests = [ 'ctags/objectivec_interface.mm.tags', 'ctags/objectivec_property.mm.tags', 'ctags/objectivec_protocol.mm.tags', + 'ctags/oop.sv.tags', 'ctags/Package.pm.tags', 'ctags/php5_5_class_kw.php.tags', 'ctags/parenthesis-rvalue.js.tags', @@ -338,6 +339,7 @@ ctags_tests = [ 'ctags/strings.php.tags', 'ctags/strings.rb.tags', 'ctags/structure.f.tags', + 'ctags/sysverilog.sv.tags', 'ctags/tabindent.py.tags', 'ctags/test.erl.tags', 'ctags/test.go.tags',
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