Branch: refs/heads/master Author: Jiří Techet techet@gmail.com Committer: GitHub noreply@github.com Date: Mon, 25 Nov 2024 16:01:48 UTC Commit: 0e5a873f0249bed118764754575c09d85acaa085 https://github.com/geany/geany/commit/0e5a873f0249bed118764754575c09d85acaa0...

Log Message: ----------- Merge pull request #4075 from cousteaulecommandant/sv

tagmanager: (System)Verilog: don't tag module of instances

Modified Paths: -------------- src/tagmanager/tm_parser.c tests/ctags/sysverilog.sv tests/ctags/sysverilog.sv.tags

Modified: src/tagmanager/tm_parser.c 7 lines changed, 5 insertions(+), 2 deletions(-) =================================================================== @@ -799,8 +799,8 @@ static TMParserMapGroup group_VERILOG[] = { {N_("Interfaces"), TM_ICON_STRUCT, tm_tag_interface_t | tm_tag_union_t}, {N_("Package"), TM_ICON_NAMESPACE, tm_tag_package_t}, {N_("Members"), TM_ICON_MEMBER, tm_tag_member_t}, - {N_("Structs"), TM_ICON_STRUCT, tm_tag_struct_t}, - {N_("Typedefs / Enums"), TM_ICON_STRUCT, tm_tag_typedef_t | tm_tag_enum_t}, + {N_("Structs / Unions / Enums"), TM_ICON_OTHER, tm_tag_struct_t | tm_tag_enum_t}, + {N_("Typedefs"), TM_ICON_STRUCT, tm_tag_typedef_t}, };

static TMParserMapEntry map_SYSVERILOG[] = { @@ -1649,6 +1649,9 @@ gboolean tm_parser_enable_role(TMParserType lang, gchar kind) * tags and we can't tell which is which just by kind. By disabling * roles for this kind, we only get package definition tags. */ return kind != 'p'; + case TM_PARSER_VERILOG: + case TM_PARSER_SYSVERILOG: + return kind != 'm'; } return TRUE; }

Modified: tests/ctags/sysverilog.sv 4 lines changed, 2 insertions(+), 2 deletions(-) =================================================================== @@ -135,9 +135,9 @@ module testbench; generate for (genvar j = 0; j < NUM_UUT; j++) begin : uut_gen logic [UUT_WIDTH-1:0] data_out; - a_module #( // NB: this SHOULDN'T be detected as a module declaration (ctags bug) + a_module #( .WIDTH (UUT_WIDTH) - ) uut ( // but this should be detected as an instance (ctags works) + ) uut ( .valid (valid_uut[j]), .* );

Modified: tests/ctags/sysverilog.sv.tags 4 lines changed, 0 insertions(+), 4 deletions(-) =================================================================== @@ -24,8 +24,6 @@ WIDTH field: a_module :: WIDTH a_module�1024�0 prototype: a_module -a_module�1024�testbench.uut_gen�0 -prototype: testbench.uut_gen :: a_module be_filtered�16384�a_module�0 variable: a_module :: be_filtered be_filtered_gen�256�a_module�0 @@ -74,8 +72,6 @@ gen_signals enumerator: generate_signals testbench :: gen_signals generate_signals�1024�0 prototype: generate_signals -generate_signals�1024�testbench�0 -prototype: testbench :: generate_signals i�16384�a_module�0 variable: a_module :: i i�16384�a_module.main_block�0

-------------- This E-Mail was brought to you by github_commit_mail.py (Source: https://github.com/geany/infrastructure).