Branch: refs/heads/master Author: Javier Mora cousteaulecommandant@gmail.com Committer: Javier Mora cousteaulecommandant@gmail.com Date: Mon, 18 Nov 2024 23:33:09 UTC Commit: bee6076de639bcadd57eef4afd426e4e20cb1a32 https://github.com/geany/geany/commit/bee6076de639bcadd57eef4afd426e4e20cb1a...
Log Message: ----------- tagmanager: SystemVerilog: map ctags
Extend SystemVerilog with additional tags supported by ctags. The tag `tm_tag_other_t` has been left unassigned for future expansion.
Modified Paths: -------------- src/tagmanager/tm_parser.c
Modified: src/tagmanager/tm_parser.c 60 lines changed, 37 insertions(+), 23 deletions(-) =================================================================== @@ -790,44 +790,58 @@ static TMParserMapGroup group_VERILOG[] = {
static TMParserMapEntry map_SYSVERILOG[] = { // Verilog and SystemVerilog - {'c', tm_tag_variable_t}, // constant - {'d', tm_tag_variable_t}, // define - {'e', tm_tag_typedef_t}, // event + {'c', tm_tag_field_t}, // constant + {'d', tm_tag_macro_t}, // define + {'e', tm_tag_variable_t}, // event {'f', tm_tag_function_t}, // function - {'m', tm_tag_class_t}, // module + {'m', tm_tag_prototype_t}, // module {'n', tm_tag_variable_t}, // net - {'p', tm_tag_variable_t}, // port + {'p', tm_tag_externvar_t}, // port {'r', tm_tag_variable_t}, // register {'t', tm_tag_function_t}, // task - {'b', tm_tag_undef_t}, // block - {'i', tm_tag_undef_t}, // instance - // SystemVerilog only (currently unused) + {'b', tm_tag_namespace_t}, // block + {'i', tm_tag_enumerator_t},// instance + // SystemVerilog only {'A', tm_tag_undef_t}, // assert - {'C', tm_tag_undef_t}, // class + {'C', tm_tag_class_t}, // class {'V', tm_tag_undef_t}, // covergroup - {'E', tm_tag_undef_t}, // enum - {'I', tm_tag_undef_t}, // interface - {'M', tm_tag_undef_t}, // modport - {'K', tm_tag_undef_t}, // package - {'P', tm_tag_undef_t}, // program - {'Q', tm_tag_undef_t}, // prototype + {'E', tm_tag_enum_t}, // enum + {'I', tm_tag_interface_t}, // interface + {'M', tm_tag_union_t}, // modport + {'K', tm_tag_package_t}, // package + {'P', tm_tag_prototype_t}, // program + {'Q', tm_tag_function_t}, // prototype {'R', tm_tag_undef_t}, // property - {'S', tm_tag_undef_t}, // struct - {'T', tm_tag_undef_t}, // typedef + {'S', tm_tag_struct_t}, // struct + {'T', tm_tag_typedef_t}, // typedef {'H', tm_tag_undef_t}, // checker {'L', tm_tag_undef_t}, // clocking {'q', tm_tag_undef_t}, // sequence - {'w', tm_tag_undef_t}, // member - {'l', tm_tag_undef_t}, // ifclass + {'w', tm_tag_member_t}, // member + {'l', tm_tag_class_t}, // ifclass {'O', tm_tag_undef_t}, // constraint - {'N', tm_tag_undef_t}, // nettype + {'N', tm_tag_typedef_t}, // nettype }; static TMParserMapGroup group_SYSVERILOG[] = { - {N_("Events"), TM_ICON_MACRO, tm_tag_typedef_t}, - {N_("Modules"), TM_ICON_CLASS, tm_tag_class_t}, + // Verilog and SystemVerilog + {N_("Modules"), TM_ICON_CLASS, tm_tag_prototype_t}, + {N_("Instances"), TM_ICON_OTHER, tm_tag_enumerator_t}, + {N_("Blocks"), TM_ICON_NAMESPACE, tm_tag_namespace_t}, {N_("Functions / Tasks"), TM_ICON_METHOD, tm_tag_function_t}, - {N_("Variables"), TM_ICON_VAR, tm_tag_variable_t}, + {N_("Macros"), TM_ICON_MACRO, tm_tag_macro_t}, + {N_("Parameters / Constants"), TM_ICON_MACRO, tm_tag_field_t}, + {N_("Ports"), TM_ICON_MEMBER, tm_tag_externvar_t}, + {N_("Signals"), TM_ICON_VAR, tm_tag_variable_t}, + // SystemVerilog only + {N_("Classes"), TM_ICON_STRUCT, tm_tag_class_t}, + {N_("Interfaces"), TM_ICON_STRUCT, tm_tag_interface_t | tm_tag_union_t}, + {N_("Package"), TM_ICON_NAMESPACE, tm_tag_package_t}, + {N_("Members"), TM_ICON_MEMBER, tm_tag_member_t}, + {N_("Structs"), TM_ICON_STRUCT, tm_tag_struct_t}, + {N_("Typedefs / Enums"), TM_ICON_STRUCT, tm_tag_typedef_t | tm_tag_enum_t}, }; +// TODO: use same group for VERILOG and SYSVERILOG for consistency (or at least same icons). +// (map has to be different since different num of elements)
static TMParserMapEntry map_R[] = { {'f', tm_tag_function_t}, // function
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