[geany/geany] 66710b: tagmanager: Unify Verilog and SystemVerilog tags - Commits

20 Nov 2024


      Branch:      refs/heads/master
Author:      Javier Mora cousteaulecommandant@gmail.com
Committer:   Javier Mora cousteaulecommandant@gmail.com
Date:        Mon, 18 Nov 2024 23:33:09 UTC
Commit:      66710b09699d416e024574bb744f80ebe09eb186
             https://github.com/geany/geany/commit/66710b09699d416e024574bb744f80ebe09eb1...
Log Message:
-----------
tagmanager: Unify Verilog and SystemVerilog tags
Use a consistent and unified map_* and group_* for Verilog and
SystemVerilog.
Some SystemVerilog features have been mirrored into Verilog,
resulting in the following changes to the latter:
- The following categories have been split:
    - constant <--> define
    - port <--> net/register
- The following categories have been merged:
    - event -><- net/register
- The following categories have been added (enabled):
    - block
    - instance
- Changes in group icons.
Note that module instantiation (in both Verilog and SystemVerilog) now
creates two ctags: one for a module definition and one for an instance.
The former should be removed, since the module isn't being defined here,
and Ctrl-click on the module name shouldn't take us here.
This needs to be fixed in ctags.
Modified Paths:
--------------
    src/tagmanager/tm_parser.c
Modified: src/tagmanager/tm_parser.c
78 lines changed, 31 insertions(+), 47 deletions(-)
===================================================================
@@ -768,40 +768,43 @@ static TMParserMapEntry map_ABC[] = {
 };
 #define group_ABC group_REST
+#define COMMON_VERILOG \
+	{'c', tm_tag_field_t},      /* constant */ \
+	{'d', tm_tag_macro_t},      /* define   */ \
+	{'e', tm_tag_variable_t},   /* event    */ \
+	{'f', tm_tag_function_t},   /* function */ \
+	{'m', tm_tag_prototype_t},  /* module   */ \
+	{'n', tm_tag_variable_t},   /* net      */ \
+	{'p', tm_tag_externvar_t},  /* port     */ \
+	{'r', tm_tag_variable_t},   /* register */ \
+	{'t', tm_tag_function_t},   /* task     */ \
+	{'b', tm_tag_namespace_t},  /* block    */ \
+	{'i', tm_tag_enumerator_t}, /* instance */
+
 static TMParserMapEntry map_VERILOG[] = {
-	{'c', tm_tag_variable_t},  // constant
-	{'d', tm_tag_variable_t},  // define
-	{'e', tm_tag_typedef_t},   // event
-	{'f', tm_tag_function_t},  // function
-	{'m', tm_tag_class_t},     // module
-	{'n', tm_tag_variable_t},  // net
-	{'p', tm_tag_variable_t},  // port
-	{'r', tm_tag_variable_t},  // register
-	{'t', tm_tag_function_t},  // task
-	{'b', tm_tag_undef_t},     // block
-	{'i', tm_tag_undef_t},     // instance
+	COMMON_VERILOG
 };
 static TMParserMapGroup group_VERILOG[] = {
-	{N_("Events"), TM_ICON_MACRO, tm_tag_typedef_t},
-	{N_("Modules"), TM_ICON_CLASS, tm_tag_class_t},
+	/* Verilog and SystemVerilog */
+	{N_("Modules"), TM_ICON_CLASS, tm_tag_prototype_t},
+	{N_("Instances"), TM_ICON_OTHER, tm_tag_enumerator_t},
+	{N_("Blocks"), TM_ICON_NAMESPACE, tm_tag_namespace_t},
    {N_("Functions / Tasks"), TM_ICON_METHOD, tm_tag_function_t},
-	{N_("Variables"), TM_ICON_VAR, tm_tag_variable_t},
+	{N_("Macros"), TM_ICON_MACRO, tm_tag_macro_t},
+	{N_("Parameters / Constants"), TM_ICON_MACRO, tm_tag_field_t},
+	{N_("Ports"), TM_ICON_MEMBER, tm_tag_externvar_t},
+	{N_("Signals"), TM_ICON_VAR, tm_tag_variable_t},
+	/* SystemVerilog only */
+	{N_("Classes"), TM_ICON_STRUCT, tm_tag_class_t},
+	{N_("Interfaces"), TM_ICON_STRUCT, tm_tag_interface_t | tm_tag_union_t},
+	{N_("Package"), TM_ICON_NAMESPACE, tm_tag_package_t},
+	{N_("Members"), TM_ICON_MEMBER, tm_tag_member_t},
+	{N_("Structs"), TM_ICON_STRUCT, tm_tag_struct_t},
+	{N_("Typedefs / Enums"), TM_ICON_STRUCT, tm_tag_typedef_t | tm_tag_enum_t},
 };
static TMParserMapEntry map_SYSVERILOG[] = {
-	// Verilog and SystemVerilog
-	{'c', tm_tag_field_t},     // constant
-	{'d', tm_tag_macro_t},     // define
-	{'e', tm_tag_variable_t},  // event
-	{'f', tm_tag_function_t},  // function
-	{'m', tm_tag_prototype_t}, // module
-	{'n', tm_tag_variable_t},  // net
-	{'p', tm_tag_externvar_t}, // port
-	{'r', tm_tag_variable_t},  // register
-	{'t', tm_tag_function_t},  // task
-	{'b', tm_tag_namespace_t}, // block
-	{'i', tm_tag_enumerator_t},// instance
-	// SystemVerilog only
+	COMMON_VERILOG
    {'A', tm_tag_undef_t},     // assert
    {'C', tm_tag_class_t},     // class
    {'V', tm_tag_undef_t},     // covergroup
@@ -822,26 +825,7 @@ static TMParserMapEntry map_SYSVERILOG[] = {
    {'O', tm_tag_undef_t},     // constraint
    {'N', tm_tag_typedef_t},   // nettype
 };
-static TMParserMapGroup group_SYSVERILOG[] = {
-	// Verilog and SystemVerilog
-	{N_("Modules"), TM_ICON_CLASS, tm_tag_prototype_t},
-	{N_("Instances"), TM_ICON_OTHER, tm_tag_enumerator_t},
-	{N_("Blocks"), TM_ICON_NAMESPACE, tm_tag_namespace_t},
-	{N_("Functions / Tasks"), TM_ICON_METHOD, tm_tag_function_t},
-	{N_("Macros"), TM_ICON_MACRO, tm_tag_macro_t},
-	{N_("Parameters / Constants"), TM_ICON_MACRO, tm_tag_field_t},
-	{N_("Ports"), TM_ICON_MEMBER, tm_tag_externvar_t},
-	{N_("Signals"), TM_ICON_VAR, tm_tag_variable_t},
-	// SystemVerilog only
-	{N_("Classes"), TM_ICON_STRUCT, tm_tag_class_t},
-	{N_("Interfaces"), TM_ICON_STRUCT, tm_tag_interface_t | tm_tag_union_t},
-	{N_("Package"), TM_ICON_NAMESPACE, tm_tag_package_t},
-	{N_("Members"), TM_ICON_MEMBER, tm_tag_member_t},
-	{N_("Structs"), TM_ICON_STRUCT, tm_tag_struct_t},
-	{N_("Typedefs / Enums"), TM_ICON_STRUCT, tm_tag_typedef_t | tm_tag_enum_t},
-};
-// TODO: use same group for VERILOG and SYSVERILOG for consistency (or at least same icons).
-// (map has to be different since different num of elements)
+#define group_SYSVERILOG group_VERILOG
static TMParserMapEntry map_R[] = {
    {'f', tm_tag_function_t},  // function
--------------
This E-Mail was brought to you by github_commit_mail.py (Source: https://github.com/geany/infrastructure).

    