Branch: refs/heads/master Author: Javier Mora cousteaulecommandant@gmail.com Committer: Javier Mora cousteaulecommandant@gmail.com Date: Mon, 18 Nov 2024 23:33:09 UTC Commit: 85564aa10dbdc8b2e47354d913c797f39fd5c4fa https://github.com/geany/geany/commit/85564aa10dbdc8b2e47354d913c797f39fd5c4...

Log Message: ----------- Split SystemVerilog keywords into type / not type

Moved all SystemVerilog keywords that are used when declaring signals to a separate `word3` category, as it was done for Verilog in PR #4037.

The list has been obtained by picking all the keywords marked as K_(EVENT|REGISTER|LOCALPARAM|PORT|PARAMETER|CONSTANT|SPECPARAM|NET) in ctags/parsers/verilog.c, extended with additional keywords from SystemVerilog-2017 section 6.7 "Net declarations" (as it was done for Verilog in PR #4037), and with `signed` and `unsigned`.

The result is a superset of the `word3` category for Verilog, extended with some keywords such as `logic`, `int`, `ref`, etc.

Modified Paths: -------------- data/filedefs/filetypes.SystemVerilog.conf

Modified: data/filedefs/filetypes.SystemVerilog.conf 4 lines changed, 2 insertions(+), 2 deletions(-) =================================================================== @@ -3,9 +3,9 @@

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$fatal $warning $error $info $fatal $warning $error $info $asserton $assertkill $assertpasson $assertfailon $assertnonvacuouson $assertoff $assertcontrol $assertpassoff $assertfailoff $assertvacuousoff $sampled $fell $changed $past_gclk $fell_gclk $changed_gclk $rising_gclk $steady_gclk $rose $stable $past $rose_gclk $stable_gclk $future_gclk $falling_gclk $changing_gclk $coverage_control $coverage_get $coverage_save $set_coverage_db_name $coverage_get_max $coverage_merge $get_coverage $load_coverage_db $random $dist_erla ng $dist_normal $dist_t $dist_chi_square $dist_exponential $dist_poisson $dist_uniform $q_initialize $q_remove $q_exam $q_add $q_full $async$and$array $async$nand$array $async$or$array $async$nor$array $sync$and$array $sync$nand$array $sync$or$array $sync$nor$array $async$and$plane $async$nand$plane $async$or$plane $async$nor$plane $sync$and$plane $sync$nand$plane $sync$or$plane $sync$nor$plane $system -word3= +word3=bit byte chandle event genvar highz0 highz1 inout input int integer interconnect large localparam logic longint medium output parameter pull0 pull1 real realtime ref reg scalared shortint shortreal signed small specparam string strong0 strong1 supply0 supply1 time tri tri0 tri1 triand trior trireg type unsigned uwire var vectored void wand weak0 weak1 wire wor docComment=

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