Branch: refs/heads/master Author: Javier Mora cousteaulecommandant@gmail.com Committer: Javier Mora cousteaulecommandant@gmail.com Date: Mon, 18 Nov 2024 23:33:09 UTC Commit: b26b7fc801316433683848da3b5d558cafcd8e5d https://github.com/geany/geany/commit/b26b7fc801316433683848da3b5d558cafcd8e...
Log Message: ----------- Add missing SystemVerilog tasks/functions
Add all tasks and functions from SystemVerilog-2017 section 21 ("Input/output system tasks and system functions") in addition to those from section 20 ("Utility system tasks and system functions").
(These were listed in a single section in the Verilog-2005 standard, but SystemVerilog split them into two sections, hence the confusion.)
Modified Paths: -------------- data/filedefs/filetypes.SystemVerilog.conf
Modified: data/filedefs/filetypes.SystemVerilog.conf 2 lines changed, 1 insertions(+), 1 deletions(-) =================================================================== @@ -4,7 +4,7 @@ [keywords] # all items must be in one line word=accept_on alias always always_comb always_ff always_latch and assert assign assume automatic before begin bind bins binsof break buf bufif0 bufif1 case casex casez cell checker class clocking cmos config const constraint context continue cover covergroup coverpoint cross deassign default defparam design disable dist do edge else end endcase endchecker endclass endclocking endconfig endfunction endgenerate endgroup endinterface endmodule endpackage endprimitive endprogram endproperty endsequence endspecify endtable endtask enum eventually expect export extends extern final first_match for force foreach forever fork forkjoin function generate global if iff ifnone ignore_bins illegal_bins implements implies import incdir include initial inside instance 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