Branch: refs/heads/master Author: Jiří Techet techet@gmail.com Committer: Jiří Techet techet@gmail.com Date: Tue, 12 Apr 2022 18:21:05 UTC Commit: 1c27f9908d0c57a98b6ce7619d9ddd88a7ff62cf https://github.com/geany/geany/commit/1c27f9908d0c57a98b6ce7619d9ddd88a7ff62...

Log Message: ----------- Add VHDL unit tests from uctags and remove the giant test.vhd

The test.vhd file is more than 8000 LOCs, it seems to be multiple concatenated VHDL sources and because of the large amount of tags, it's hard to see the changes.

Modified Paths: -------------- tests/ctags/Makefile.am tests/ctags/test.vhd tests/ctags/test.vhd.tags tests/ctags/vhdl-component.vhd tests/ctags/vhdl-component.vhd.tags tests/ctags/vhdl-local.vhd tests/ctags/vhdl-local.vhd.tags tests/ctags/vhdl-port.vhd tests/ctags/vhdl-port.vhd.tags tests/ctags/vhdl-process.vhd tests/ctags/vhdl-process.vhd.tags tests/ctags/vhdl-type.vhd tests/ctags/vhdl-type.vhd.tags tests/meson.build

Modified: tests/ctags/Makefile.am 6 lines changed, 5 insertions(+), 1 deletions(-) =================================================================== @@ -327,7 +327,6 @@ test_sources = \ test.erl \ test.go \ test.py \ - test.vhd \ test_input.rs \ test_input2.rs \ titles.t2t \ @@ -337,6 +336,11 @@ test_sources = \ union.f \ value.f \ var-and-return-type.cpp \ + vhdl-component.vhd \ + vhdl-local.vhd \ + vhdl-port.vhd \ + vhdl-process.vhd \ + vhdl-type.vhd \ whitespaces.php \ $(NULL) test_results = $(test_sources:=.tags)

Modified: tests/ctags/test.vhd 8174 lines changed, 0 insertions(+), 8174 deletions(-) =================================================================== No diff available, check online

Modified: tests/ctags/test.vhd.tags 358 lines changed, 0 insertions(+), 358 deletions(-) =================================================================== @@ -1,358 +0,0 @@ -# format=tagmanager -ADly�16384�0 -AND2�1�0 -AND2�64�0 -AtcStatusReg�16384�0 -BDly�16384�0 -BIDIR�1�0 -BIDIR�64�0 -B_Busy�16384�0 -Backoff�16384�0 -BidirBuf�1�0 -BidirBuf�64�0 -BidirCnt�1�0 -CaptureOutputs�16384�0 -ClkDly�16384�0 -ClkPeriod�16384�0 -Cnt�16384�0 -Cnt4Term�1�0 -Cnt4Term�64�0 -CntL�16384�0 -CntVal�16384�0 -Const�16384�0 -Counter�1�0 -CtrlBits�4096�0 -CtrlRegRange�16384�0 -DEC2x4�16�0 -DFF�1�0 -DFFE�1�0 -DFFE�64�0 -DFFE_SR�1�0 -DFFE_SR�64�0 -DLATCHH�1�0 -DLATCHH�64�0 -DelayMux�64�0 -Dont_Care�16384�0 -ErrorMsg�16384�0 -ErrorMsgLine�16384�0 -FEWGATES�1�0 -FlopOut�16384�0 -ForceShare�1�0 -FoundError�16384�0 -GatesPkg�256�0 -INVERTER�1�0 -INVERTER�64�0 -Idle�16384�0 -IntCtrlReg�16384�0 -IoIntStatReg�16384�0 -LPCI_Devsel_n�16384�0 -LPCI_Stop_n�16384�0 -LPCI_Trdy_n�16384�0 -Latc_stat_rd_n�16384�0 -Lint_ctrl_rd_n�16384�0 -Lio_int_stat_rd_n�16384�0 -Lmgmt_stat_rd_n�16384�0 -LoadCnt�1�0 -LoadCnt�64�0 -LoadVal�16384�0 -LogicFcn�1�0 -LoopCount�16384�0 -LoopStim�64�0 -Lrst_ctrl_rd_n�16384�0 -Lsio_dec_n�16384�0 -MgmtStatusReg�16384�0 -NumVectors�16384�0 -OR2�1�0 -OR2�64�0 -OrGate�16384�0 -OrGateDly�16384�0 -Pow�16�0 -Power�1�0 -Power�64�0 -PowerPkg�256�0 -PropDelay�16384�0 -Qout�16384�0 -Result�16384�0 -RollVal�16�0 -RstCtrlReg�16384�0 -SRFF�1�0 -S_Data�16384�0 -SimDFF�1�0 -SimDFF�64�0 -SimLoopDelay�16384�0 -SimModel�2048�0 -StimInputs�16384�0 -SuperIoRange�16384�0 -THREE�16384�0 -TRIBUF�1�0 -TRIBUF�64�0 -TRIBUF8�1�0 -TempVector�16384�0 -TestClk�16384�0 -Turn_Ar�16384�0 -VectorLine�16384�0 -VectorValid�16384�0 -a_and_b�16384�0 -accumL�16384�0 -accumulate�64�0 -accumulator�1�0 -adder�1�0 -andSignal�16384�0 -andTerm�16384�0 -asyncLdCnt�1�0 -asyncLoad�1�0 -atc_stat_rd_n�4096�0 -bad_charcode�16384�0 -basic�2048�0 -bcd2sevSeg�64�0 -behav�2048�0 -behave�2048�0 -behavior�2048�0 -behavioral�2048�0 -behaviour�2048�0 -bidirBuf�64�0 -bidirbuffer�1�0 -bitpos�16384�0 -body�256�0 -c�16384�0 -c_and_d�16384�0 -carry�16384�0 -char2char_t�4096�0 -charcode�16384�0 -charpos�16384�0 -clkGen�1�0 -clkTable�16384�0 -clkTableType�4096�0 -cnt�16384�0 -cntL�16384�0 -compare�1�0 -compare�64�0 -compareDC�1�0 -concat�2048�0 -concurrent�2048�0 -convertArith�1�0 -count8�1�0 -countL�16384�0 -counter�1�0 -counter�64�0 -curStProc�64�0 -currStProc�64�0 -currState�16384�0 -d�16384�0 -dataflow�2048�0 -decProcs�256�0 -decoder�1�0 -decoder�64�0 -decrement�64�0 -delayCnt�16384�0 -delayCntVal�16384�0 -delayReg�64�0 -delayreg�64�0 -demo�64�0 -dff�16�0 -dffTri�1�0 -digit�16384�0 -digit2int_t�4096�0 -done�16384�0 -downCnt�16384�0 -downCntData�16384�0 -downCntEn�16384�0 -downCntL�16384�0 -downCntLd�16384�0 -downCntr�64�0 -downCounter�1�0 -enable�64�0 -encode�64�0 -encoder�1�0 -endPulse�16384�0 -equalProc�64�0 -f_logic_to_character�16384�0 -f_logic_to_character_t�4096�0 -fcn�64�0 -flipFlop�1�0 -fsm�2048�0 -fsmType�4096�0 -funky�2048�0 -genXor�16384�0 -goodlength�16384�0 -hex_bits_per_digit�16384�0 -hex_logic_vector�16384�0 -hex_logic_vector_t�4096�0 -hexdigit2int�16384�0 -hexint2logic�16384�0 -hexint2logic_t�4096�0 -hierarchical�2048�0 -i�16384�0 -increment�64�0 -index�16384�0 -inputValInt�16384�0 -instance�2048�0 -int2hexdigit�16384�0 -int2hexdigit_t�4096�0 -int2octdigit�16384�0 -int2octdigit_t�4096�0 -int_ctrl_rd_n�4096�0 -integer_value�16384�0 -io1164�256�0 -io_int_stat_rd_n�4096�0 -isa_dec�1�0 -isx�16384�0 -la_n�16384�0 -lastAssignment�1�0 -lb_n�16384�0 -lc_n�16384�0 -ld_n�16384�0 -le_n�16384�0 -lengthReg�64�0 -lf_n�16384�0 -lg_n�16384�0 -loadCnt�1�0 -loadCnt�64�0 -loadCntTB�1�0 -loadDelayCnt�16384�0 -loadLengthCnt�16384�0 -loadVal�16384�0 -localRst�16384�0 -localSum�16384�0 -localY�16384�0 -logic_value�16384�0 -lookupTable�64�0 -loopDemo�2048�0 -loopXor�16384�0 -lowcase�16384�0 -m�16384�0 -maxhex_charcode�16384�0 -maxoct_charcode�16384�0 -mgmt_stat_rd_n�4096�0 -multiDriver�2048�0 -multiplier�1�0 -mux�1�0 -nextStProc�64�0 -nextState�16384�0 -notA�16384�0 -notB�16384�0 -not_c_and_d�16384�0 -numClks�4096�0 -numPatterns�4096�0 -nxtStProc�64�0 -oct_bits_per_digit�16384�0 -oct_logic_vector�16384�0 -oct_logic_vector_t�4096�0 -octdigit2int�16384�0 -octint2logic�16384�0 -octint2logic_t�4096�0 -oddParityGen�1�0 -oddParityLoop�1�0 -oe�16384�0 -old_l�16384�0 -one�16384�0 -outConProc�64�0 -outputs�64�0 -pAdderAttr�1�0 -paramDFF�1�0 -parameterize�2048�0 -pci_target�1�0 -pos�16384�0 -powerL�16384�0 -powerOfFour�1�0 -primitive�256�0 -priority_encoder�1�0 -progPulse�1�0 -progPulseFsm�1�0 -progPulseFsmType�4096�0 -pulse�64�0 -pulseCnt�16384�0 -pulseCntVal�16384�0 -pulseDelay�64�0 -pulseErr�1�0 -pulseLength�64�0 -pulseOutput�64�0 -q�16384�0 -qLocal�16384�0 -qualify�64�0 -read�16�0 -readVec�64�0 -read_hex�16�0 -read_oct�16�0 -reg�64�0 -reg�4096�0 -reg�16384�0 -regArray�4096�0 -regFile�1�0 -regProc�64�0 -registerFile�16384�0 -resFcnDemo�1�0 -resetLatch�64�0 -result�16384�0 -rst_ctrl_rd_n�4096�0 -rtl�2048�0 -scalable�2048�0 -scaleDFF�1�0 -scaleUpCnt�1�0 -scaleUpCnt�64�0 -scaleable�256�0 -scaleable�2048�0 -selectIn�16384�0 -sequential�2048�0 -sevenSegment�1�0 -sevenSegment�64�0 -sevenSegmentTB�1�0 -shift�64�0 -shifter�1�0 -signalDemo�1�0 -simHierarchy�1�0 -simModel�2048�0 -simPrimitives�256�0 -simple�2048�0 -sio_dec_n�4096�0 -stage0�16384�0 -stage1�16384�0 -stage2�16384�0 -stage3�16384�0 -stage4�16384�0 -startPulse�16384�0 -stateBits�4096�0 -stateTable�16384�0 -stateVec�4096�0 -struct_dffe�1�0 -struct_dffe_sr�1�0 -struct_dlatch�1�0 -structural�2048�0 -success�16384�0 -sum�64�0 -synthesis�2048�0 -tCQ�16384�0 -tH�16384�0 -tPD_A�16384�0 -tPD_B�16384�0 -tPD_Sel�16384�0 -tS�16384�0 -targetFsmType�4096�0 -tempSum�16384�0 -termCnt�16384�0 -test�1�0 -testVector�16384�0 -testbench�2048�0 -tri�16384�0 -tribufArrayType�4096�0 -tribufType�4096�0 -tribuffer�1�0 -typeConvert�1�0 -unnamed�64�0 -upper�4096�0 -vData�16384�0 -vLoad�16384�0 -vQ�16384�0 -vRst�16384�0 -vector�4096�0 -vectorArray�4096�0 -vectorTable�16384�0 -vectorType�4096�0 -verify�64�0 -waitDelayEnd�16384�0 -waitLengthEnd�16384�0 -wontWork�2048�0 -write�16�0 -write_hex�16�0 -write_oct�16�0 -x_charcode�16384�0

Modified: tests/ctags/vhdl-component.vhd 54 lines changed, 54 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,54 @@ +-- Taken from a comment https://github.com/universal-ctags/ctags/issues/2678 +-- submitted by @pidgeon777 +library ieee; +use ieee.std_logic_1164.all; + +entity ENTITY_TOP is + generic ( + GEN : integer := 0 + ); + port ( + INP : in std_logic + ); +end entity; + +architecture arch of ENTITY_TOP is + signal sig : std_logic := '0'; + + component ENTITY_1 + generic ( + GEN : integer := 0 + ); + port ( + INP : in std_logic + ); + end component; + + component ENTITY_2 + generic ( + GEN : integer := 0 + ); + port ( + INP : in std_logic + ); + end component; + +begin + + ENTITY_1_i : ENTITY_1 + generic map( + GEN => 0 + ) + port map( + INP => '0' + ); + + ENTITY_2_i : ENTITY_2 + generic map( + GEN => 0 + ) + port map( + INP => '0' + ); + +end architecture;

Modified: tests/ctags/vhdl-component.vhd.tags 6 lines changed, 6 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,6 @@ +# format=tagmanager +ENTITY_1�64�0 +ENTITY_2�64�0 +ENTITY_TOP�1�0 +arch�2048�0 +sig�16384�0

Modified: tests/ctags/vhdl-local.vhd 203 lines changed, 203 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,203 @@ +-- +-- Taken from rtl/commonlib/types_util.vhd of https://github.com/sergeykhbr/riscv_vhdl +-- +----------------------------------------------------------------------------- +--! @file +--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved. +--! @author Sergey Khabarov - sergeykhbr@gmail.com +--! @brief Package for common testbenches implementation. +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library std; +use std.textio.all; + +package types_util is + +function strlen(s: in string) return integer; +function StringToUVector(inStr: string) return std_ulogic_vector; +function StringToSVector(inStr: string) return std_logic_vector; +function UnsignedToSigned(inUnsigned: std_ulogic_vector) return std_logic_vector; +function SignalFromString(inStr: string; ind : integer ) return std_logic; +function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector; + +function tost(v:std_logic_vector) return string; +function tost(v:std_logic) return string; +function tost(i : integer) return string; +procedure print(s : string); + +end; + +package body types_util is + + function strlen(s: in string) return integer is + variable n: integer:=0; variable sj: integer:=s'left; + begin + loop + if sj>s'right then exit; + elsif s(sj)=NUL then exit; --sequential if protects sj > length + else sj:=sj+1; n:=n+1; + end if; + end loop; + return n; + end strlen; + + function SignalFromString(inStr: string; ind : integer ) return std_logic is + variable temp: std_logic := 'X'; + begin + if(inStr(inStr'high-ind)='1') then temp := '1'; + elsif(inStr(inStr'high-ind)='0') then temp := '0'; + end if; + return temp; + end function SignalFromString; + + + function StringToUVector(inStr: string) return std_ulogic_vector is + variable temp: std_ulogic_vector(inStr'range) := (others => 'X'); + begin + for i in inStr'range loop -- + if(inStr(inStr'high-i+1)='1') then temp(i) := '1'; + elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0'; + end if; + end loop; + return temp(inStr'high downto 1); + end function StringToUVector; + -- conversion function + + function StringToSVector(inStr: string) return std_logic_vector is + variable temp: std_logic_vector(inStr'range) := (others => 'X'); + begin + for i in inStr'range loop -- + if(inStr(inStr'high-i+1)='1') then temp(i) := '1'; + elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0'; + end if; + end loop; + return temp(inStr'high downto 1); + end function StringToSVector; + + function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector is + constant ss: string(1 to inStr'length) := inStr; + variable c : integer; + variable temp: std_logic_vector(7 downto 0) := (others => 'X'); + begin + c := character'pos(ss(idx+1)); + for i in 0 to 7 loop -- + temp(i) := to_unsigned(c,8)(i); + end loop; + return temp; + end function SymbolToSVector; + + + function UnsignedToSigned(inUnsigned: std_ulogic_vector) + return std_logic_vector is + variable temp: std_logic_vector(inUnsigned'length-1 downto 0) := (others => 'X'); + variable i: integer:=0; + begin + while i < inUnsigned'length loop + if(inUnsigned(i)='1') then temp(i) := '1'; + elsif(inUnsigned(i)='0') then temp(i) := '0'; + end if; + i := i+1; + end loop; + return temp; + end function UnsignedToSigned; + + + subtype nibble is std_logic_vector(3 downto 0); + + function todec(i:integer) return character is + begin + case i is + when 0 => return('0'); + when 1 => return('1'); + when 2 => return('2'); + when 3 => return('3'); + when 4 => return('4'); + when 5 => return('5'); + when 6 => return('6'); + when 7 => return('7'); + when 8 => return('8'); + when 9 => return('9'); + when others => return('0'); + end case; + end; + + + function tohex(n:nibble) return character is + begin + case n is + when "0000" => return('0'); + when "0001" => return('1'); + when "0010" => return('2'); + when "0011" => return('3'); + when "0100" => return('4'); + when "0101" => return('5'); + when "0110" => return('6'); + when "0111" => return('7'); + when "1000" => return('8'); + when "1001" => return('9'); + when "1010" => return('a'); + when "1011" => return('b'); + when "1100" => return('c'); + when "1101" => return('d'); + when "1110" => return('e'); + when "1111" => return('f'); + when others => return('X'); + end case; + end; + + + function tost(v:std_logic_vector) return string is + constant vlen : natural := v'length; --' + constant slen : natural := (vlen+3)/4; + variable vv : std_logic_vector(0 to slen*4-1) := (others => '0'); + variable s : string(1 to slen); + variable nz : boolean := false; + variable index : integer := -1; + begin + vv(slen*4-vlen to slen*4-1) := v; + for i in 0 to slen-1 loop + if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then + index := i; + else + nz := false; + s(i+1) := tohex(vv(i*4 to i*4+3)); + end if; + end loop; + if ((index +2) = slen) then return(s(slen to slen)); + else return(string'("0x") & s(index+2 to slen)); end if; --' + end; + + + function tost(v:std_logic) return string is + begin + if to_x01(v) = '1' then return("1"); else return("0"); end if; + end; + + + function tost(i : integer) return string is + variable L : line; + variable s, x : string(1 to 128); + variable n, tmp : integer := 0; + begin + tmp := i; + if i < 0 then tmp := -i; end if; + loop + s(128-n) := todec(tmp mod 10); + tmp := tmp / 10; + n := n+1; + if tmp = 0 then exit; end if; + end loop; + x(1 to n) := s(129-n to 128); + if i < 0 then return "-" & x(1 to n); end if; + return(x(1 to n)); + end; + + procedure print(s : string) is + variable L : line; + begin + L := new string'(s); writeline(output, L); + end; + +end;

Modified: tests/ctags/vhdl-local.vhd.tags 27 lines changed, 27 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,27 @@ +# format=tagmanager +L�16384�0 +SignalFromString�16�0 +StringToSVector�16�0 +StringToUVector�16�0 +SymbolToSVector�16�0 +UnsignedToSigned�16�0 +body�256�0 +c�16384�0 +i�16384�0 +index�16384�0 +n�16384�0 +nibble�4096�0 +nz�16384�0 +print�16�0 +s�16384�0 +sj�16384�0 +slen�16384�0 +ss�16384�0 +strlen�16�0 +temp�16384�0 +todec�16�0 +tohex�16�0 +tost�16�0 +types_util�256�0 +vlen�16384�0 +vv�16384�0

Modified: tests/ctags/vhdl-port.vhd 5 lines changed, 5 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,5 @@ +-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf +entity logical_ops_1 is + port (a, b, c, d: in bit; + m: out bit); +end logical_ops_1;

Modified: tests/ctags/vhdl-port.vhd.tags 2 lines changed, 2 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,2 @@ +# format=tagmanager +logical_ops_1�1�0

Modified: tests/ctags/vhdl-process.vhd 51 lines changed, 51 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,51 @@ +-- +-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl +-- +----------------------------------------------------------------------------- +--! @file +--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved. +--! @author Sergey Khabarov - sergeykhbr@gmail.com +--! @brief Stack trace buffer on hardware level. +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +library commonlib; +use commonlib.types_common.all; + +entity StackTraceBuffer is + generic ( + abits : integer := 5; + dbits : integer := 64 + ); + port ( + i_clk : in std_logic; + i_raddr : in std_logic_vector(abits-1 downto 0); + o_rdata : out std_logic_vector(dbits-1 downto 0); + i_we : in std_logic; + i_waddr : in std_logic_vector(abits-1 downto 0); + i_wdata : in std_logic_vector(dbits-1 downto 0) + ); +end; + +architecture arch_StackTraceBuffer of StackTraceBuffer is + + type ram_type is array ((2**abits)-1 downto 0) of std_logic_vector (dbits-1 downto 0); + signal stackbuf : ram_type; + signal raddr : std_logic_vector(abits-1 downto 0); + +begin + + -- registers: + regs : process(i_clk) begin + if rising_edge(i_clk) then + if i_we = '1' then + stackbuf(conv_integer(i_waddr)) <= i_wdata; + end if; + raddr <= i_raddr; + end if; + end process; + + o_rdata <= stackbuf(conv_integer(raddr)); + +end;

Modified: tests/ctags/vhdl-process.vhd.tags 7 lines changed, 7 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,7 @@ +# format=tagmanager +StackTraceBuffer�1�0 +arch_StackTraceBuffer�2048�0 +raddr�16384�0 +ram_type�4096�0 +regs�64�0 +stackbuf�16384�0

Modified: tests/ctags/vhdl-type.vhd 325 lines changed, 325 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,325 @@ +-- +-- Taken from rtl/misclib/types_misc.vhd of https://github.com/sergeykhbr/riscv_vhdl +-- +--! +--! Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com +--! +--! Licensed under the Apache License, Version 2.0 (the "License"); +--! you may not use this file except in compliance with the License. +--! You may obtain a copy of the License at +--! +--! http://www.apache.org/licenses/LICENSE-2.0 +--! Unless required by applicable law or agreed to in writing, software +--! distributed under the License is distributed on an "AS IS" BASIS, +--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +--! See the License for the specific language governing permissions and +--! limitations under the License. +--! + +--! Standard library. +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library commonlib; +use commonlib.types_common.all; +--! Technology definition library. +library techmap; +use techmap.gencomp.all; +--! CPU, System Bus and common peripheries library. +library ambalib; +use ambalib.types_amba4.all; +use ambalib.types_bus0.all; + +--! @brief Declaration of components visible on SoC top level. +package types_misc is + +--! @defgroup irq_id_group AXI4 interrupt generic IDs. +--! @ingroup axi4_config_generic_group +--! @details Unique indentificator of the interrupt pin also used +--! as an index in the interrupts bus. +--! @{ + +--! Zero interrupt index must be unused. +constant CFG_IRQ_UNUSED : integer := 0; +--! UART_A interrupt pin. +constant CFG_IRQ_UART1 : integer := 1; +--! Ethernet MAC interrupt pin. +constant CFG_IRQ_ETHMAC : integer := 2; +--! GP Timers interrupt pin +constant CFG_IRQ_GPTIMERS : integer := 3; +--! GNSS Engine IRQ pin that generates 1 msec pulses. +constant CFG_IRQ_GNSSENGINE : integer := 4; +--! Total number of used interrupts in a system +constant CFG_IRQ_TOTAL : integer := 5; +--! @} + +--! @brief SOC global reset former. +--! @details This module produces output reset signal in a case if +--! button 'Reset' was pushed or PLL isn't a 'lock' state. +--! param[in] inSysReset Button generated signal +--! param[in] inSysClk Clock from the PLL. Bus clock. +--! param[out] outReset Output reset signal with active 'High' (1 = reset). +component reset_global +port ( + inSysReset : in std_ulogic; + inSysClk : in std_ulogic; + outReset : out std_ulogic ); +end component; + + +--! Boot ROM with AXI4 interface declaration. +component axi4_rom is +generic ( + memtech : integer := inferred; + async_reset : boolean := false; + xaddr : integer := 0; + xmask : integer := 16#fffff#; + sim_hexfile : string + ); +port ( + clk : in std_logic; + nrst : in std_logic; + cfg : out axi4_slave_config_type; + i : in axi4_slave_in_type; + o : out axi4_slave_out_type + ); +end component; + +--! Internal RAM with AXI4 interface declaration. +component axi4_sram is + generic ( + memtech : integer := inferred; + async_reset : boolean := false; + xaddr : integer := 0; + xmask : integer := 16#fffff#; + abits : integer := 17; + init_file : string := "" -- only for 'inferred' + ); + port ( + clk : in std_logic; + nrst : in std_logic; + cfg : out axi4_slave_config_type; + i : in axi4_slave_in_type; + o : out axi4_slave_out_type + ); +end component; + +--! AXI4 to SPI brdige for external Flash IC Micron M25AA1024 +type spi_in_type is record + SDI : std_logic; +end record; + +type spi_out_type is record + SDO : std_logic; + SCK : std_logic; + nCS : std_logic; + nWP : std_logic; + nHOLD : std_logic; + RESET : std_logic; +end record; + +constant spi_out_none : spi_out_type := ( + '0', '0', '1', '1', '1', '0' +); + +component axi4_flashspi is + generic ( + async_reset : boolean := false; + xaddr : integer := 0; + xmask : integer := 16#fffff#; + wait_while_write : boolean := true -- hold AXI bus response until end of write cycle + ); + port ( + clk : in std_logic; + nrst : in std_logic; + cfg : out axi4_slave_config_type; + i_spi : in spi_in_type; + o_spi : out spi_out_type; + i_axi : in axi4_slave_in_type; + o_axi : out axi4_slave_out_type ); +end component; + +--! @brief AXI4 GPIO controller +component axi4_gpio is + generic ( + async_reset : boolean := false; + xaddr : integer := 0; + xmask : integer := 16#fffff#; + xirq : integer := 0; + width : integer := 12 + ); + port ( + clk : in std_logic; + nrst : in std_logic; + cfg : out axi4_slave_config_type; + i : in axi4_slave_in_type; + o : out axi4_slave_out_type; + i_gpio : in std_logic_vector(width-1 downto 0); + o_gpio : out std_logic_vector(width-1 downto 0); + o_gpio_dir : out std_logic_vector(width-1 downto 0) + ); +end component; + +type uart_in_type is record + rd : std_ulogic; + cts : std_ulogic; +end record; + +type uart_out_type is record + td : std_ulogic; + rts : std_ulogic; +end record; + +--! UART with the AXI4 interface declaration. +component axi4_uart is + generic ( + async_reset : boolean := false; + xaddr : integer := 0; + xmask : integer := 16#fffff#; + xirq : integer := 0; + fifosz : integer := 16 + ); + port ( + clk : in std_logic; + nrst : in std_logic; + cfg : out axi4_slave_config_type; + i_uart : in uart_in_type; + o_uart : out uart_out_type; + i_axi : in axi4_slave_in_type; + o_axi : out axi4_slave_out_type; + o_irq : out std_logic); +end component; + +--! Test Access Point via UART (debug access) +component uart_tap is + port ( + nrst : in std_logic; + clk : in std_logic; + i_uart : in uart_in_type; + o_uart : out uart_out_type; + i_msti : in axi4_master_in_type; + o_msto : out axi4_master_out_type; + o_mstcfg : out axi4_master_config_type + ); +end component; + +-- JTAG TAP +component tap_jtag is + generic ( + ainst : integer range 0 to 255 := 2; + dinst : integer range 0 to 255 := 3); + port ( + nrst : in std_logic; + clk : in std_logic; + i_tck : in std_logic; -- in: Test Clock + i_ntrst : in std_logic; -- in: + i_tms : in std_logic; -- in: Test Mode State + i_tdi : in std_logic; -- in: Test Data Input + o_tdo : out std_logic; -- out: Test Data Output + o_jtag_vref : out std_logic; + i_msti : in axi4_master_in_type; + o_msto : out axi4_master_out_type; + o_mstcfg : out axi4_master_config_type + ); +end component; + + +--! @brief Interrupt controller with the AXI4 interface declaration. +--! @details To rise interrupt on certain CPU HostIO interface is used. +component axi4_irqctrl is + generic ( + async_reset : boolean := false; + xaddr : integer := 0; + xmask : integer := 16#fffff# + ); + port + ( + clk : in std_logic; + nrst : in std_logic; + i_irqs : in std_logic_vector(CFG_IRQ_TOTAL-1 downto 1); + o_cfg : out axi4_slave_config_type; + i_axi : in axi4_slave_in_type; + o_axi : out axi4_slave_out_type; + o_irq_meip : out std_logic + ); + end component; + + --! @brief General Purpose Timers with the AXI interface. + --! @details This module provides high precision counter and + --! generic number of GP timers. + component axi4_gptimers is + generic ( + async_reset : boolean := false; + xaddr : integer := 0; + xmask : integer := 16#fffff#; + xirq : integer := 0; + tmr_total : integer := 2 + ); + port ( + clk : in std_logic; + nrst : in std_logic; + cfg : out axi4_slave_config_type; + i_axi : in axi4_slave_in_type; + o_axi : out axi4_slave_out_type; + o_pwm : out std_logic_vector(tmr_total-1 downto 0); + o_irq : out std_logic + ); + end component; + +--! @brief Plug-n-Play support module with AXI4 interface declaration. +--! @details Each device in a system hase to implements sideband signal +--! structure 'nasti_slave_config_type' that allows FW to +--! detect Hardware configuration in a run-time. +--! @todo Implements PnP signals for all Masters devices. +component axi4_pnp is + generic ( + async_reset : boolean := false; + xaddr : integer := 0; + xmask : integer := 16#fffff#; + tech : integer := 0; + hw_id : std_logic_vector(31 downto 0) := X"20170101" + ); + port ( + sys_clk : in std_logic; + adc_clk : in std_logic; + nrst : in std_logic; + mstcfg : in bus0_xmst_cfg_vector; + slvcfg : in bus0_xslv_cfg_vector; + cfg : out axi4_slave_config_type; + i : in axi4_slave_in_type; + o : out axi4_slave_out_type; + -- OTP Timing control + i_otp_busy : in std_logic; + o_otp_cfg_rsetup : out std_logic_vector(3 downto 0); + o_otp_cfg_wadrsetup : out std_logic_vector(3 downto 0); + o_otp_cfg_wactive : out std_logic_vector(31 downto 0); + o_otp_cfg_whold : out std_logic_vector(3 downto 0) + ); +end component; + +component axi4_otp is + generic ( + async_reset : boolean := false; + xaddr : integer := 0; + xmask : integer := 16#ffffe# + ); + port ( + clk : in std_logic; + nrst : in std_logic; + cfg : out axi4_slave_config_type; + i_axi : in axi4_slave_in_type; + o_axi : out axi4_slave_out_type; + o_otp_we : out std_ulogic; + o_otp_re : out std_ulogic; + o_otp_addr : out std_logic_vector(11 downto 0); + o_otp_wdata : out std_logic_vector(15 downto 0); + i_otp_rdata : in std_logic_vector(15 downto 0); + i_cfg_rsetup : in std_logic_vector(3 downto 0); + i_cfg_wadrsetup : in std_logic_vector(3 downto 0); + i_cfg_wactive : in std_logic_vector(31 downto 0); + i_cfg_whold : in std_logic_vector(3 downto 0); + o_busy : out std_logic + ); +end component; + +end; -- package declaration

Modified: tests/ctags/vhdl-type.vhd.tags 25 lines changed, 25 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,25 @@ +# format=tagmanager +CFG_IRQ_ETHMAC�16384�0 +CFG_IRQ_GNSSENGINE�16384�0 +CFG_IRQ_GPTIMERS�16384�0 +CFG_IRQ_TOTAL�16384�0 +CFG_IRQ_UART1�16384�0 +CFG_IRQ_UNUSED�16384�0 +axi4_flashspi�64�0 +axi4_gpio�64�0 +axi4_gptimers�64�0 +axi4_irqctrl�64�0 +axi4_otp�64�0 +axi4_pnp�64�0 +axi4_rom�64�0 +axi4_sram�64�0 +axi4_uart�64�0 +reset_global�64�0 +spi_in_type�4096�0 +spi_out_none�16384�0 +spi_out_type�4096�0 +tap_jtag�64�0 +types_misc�256�0 +uart_in_type�4096�0 +uart_out_type�4096�0 +uart_tap�64�0

Modified: tests/meson.build 6 lines changed, 5 insertions(+), 1 deletions(-) =================================================================== @@ -323,7 +323,6 @@ ctags_tests = files([ 'ctags/test.erl.tags', 'ctags/test.go.tags', 'ctags/test.py.tags', - 'ctags/test.vhd.tags', 'ctags/test_input.rs.tags', 'ctags/test_input2.rs.tags', 'ctags/titles.t2t.tags', @@ -333,6 +332,11 @@ ctags_tests = files([ 'ctags/union.f.tags', 'ctags/value.f.tags', 'ctags/var-and-return-type.cpp.tags', + 'ctags/vhdl-component.vhd.tags', + 'ctags/vhdl-local.vhd.tags', + 'ctags/vhdl-port.vhd.tags', + 'ctags/vhdl-process.vhd.tags', + 'ctags/vhdl-type.vhd.tags', 'ctags/whitespaces.php.tags' ])

-------------- This E-Mail was brought to you by github_commit_mail.py (Source: https://github.com/geany/infrastructure).