Branch: refs/heads/master Author: Javier Mora cousteaulecommandant@gmail.com Committer: Javier Mora cousteaulecommandant@gmail.com Date: Sun, 24 Nov 2024 23:18:23 UTC Commit: a7ae4b583ebebe6aa056edbe1e640d71493b1753 https://github.com/geany/geany/commit/a7ae4b583ebebe6aa056edbe1e640d71493b17...

Log Message: ----------- tagmanager: Verilog: don't tag module of instances

Currently, for a Verilog line like `a_module inst (clk, d, q);`, ctags will emit both an "instance" tag and a "module" reference, which Geany incorrectly interprets as a module definition.

Disable ctags roles for Verilog (and SystemVerilog) modules to prevent this.

Modified Paths: -------------- src/tagmanager/tm_parser.c tests/ctags/sysverilog.sv tests/ctags/sysverilog.sv.tags

Modified: src/tagmanager/tm_parser.c 3 lines changed, 3 insertions(+), 0 deletions(-) =================================================================== @@ -1649,6 +1649,9 @@ gboolean tm_parser_enable_role(TMParserType lang, gchar kind) * tags and we can't tell which is which just by kind. By disabling * roles for this kind, we only get package definition tags. */ return kind != 'p'; + case TM_PARSER_VERILOG: + case TM_PARSER_SYSVERILOG: + return kind != 'm'; } return TRUE; }

Modified: tests/ctags/sysverilog.sv 4 lines changed, 2 insertions(+), 2 deletions(-) =================================================================== @@ -135,9 +135,9 @@ module testbench; generate for (genvar j = 0; j < NUM_UUT; j++) begin : uut_gen logic [UUT_WIDTH-1:0] data_out; - a_module #( // NB: this SHOULDN'T be detected as a module declaration (ctags bug) + a_module #( .WIDTH (UUT_WIDTH) - ) uut ( // but this should be detected as an instance (ctags works) + ) uut ( .valid (valid_uut[j]), .* );

Modified: tests/ctags/sysverilog.sv.tags 4 lines changed, 0 insertions(+), 4 deletions(-) =================================================================== @@ -24,8 +24,6 @@ WIDTH field: a_module :: WIDTH a_module�1024�0 prototype: a_module -a_module�1024�testbench.uut_gen�0 -prototype: testbench.uut_gen :: a_module be_filtered�16384�a_module�0 variable: a_module :: be_filtered be_filtered_gen�256�a_module�0 @@ -74,8 +72,6 @@ gen_signals enumerator: generate_signals testbench :: gen_signals generate_signals�1024�0 prototype: generate_signals -generate_signals�1024�testbench�0 -prototype: testbench :: generate_signals i�16384�a_module�0 variable: a_module :: i i�16384�a_module.main_block�0

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