Branch: refs/heads/master Author: Javier Mora cousteaulecommandant@gmail.com Committer: Javier Mora cousteaulecommandant@gmail.com Date: Mon, 18 Nov 2024 23:33:09 UTC Commit: 4b7c56e5f482d2fb562fe81bd45b8641c5642828 https://github.com/geany/geany/commit/4b7c56e5f482d2fb562fe81bd45b8641c56428...

Log Message: ----------- Add SystemVerilog ctags unit tests

Added two ctags unit tests for SystemVerilog: one with a "normal" design (an executable testbench) to exercise logic and simulation constructs, and one with a package and several OOP-related constructs.

It should be noted that some incorrect behavior has been found in ctags when writing the tests; these were written down as comments in the test files, and should be fixed in upstream ctags.

Modified Paths: -------------- tests/ctags/Makefile.am tests/ctags/oop.sv tests/ctags/oop.sv.tags tests/ctags/sysverilog.sv tests/ctags/sysverilog.sv.tags tests/meson.build

Modified: tests/ctags/Makefile.am 2 lines changed, 2 insertions(+), 0 deletions(-) =================================================================== @@ -263,6 +263,7 @@ test_sources = \ objectivec_interface.mm \ objectivec_property.mm \ objectivec_protocol.mm \ + oop.sv \ Package.pm \ php5_5_class_kw.php \ parenthesis-rvalue.js \ @@ -341,6 +342,7 @@ test_sources = \ strings.php \ strings.rb \ structure.f \ + sysverilog.sv \ tabindent.py \ test.erl \ test.go \

Modified: tests/ctags/oop.sv 145 lines changed, 145 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,145 @@ +/* Tests the following SystemVerilog ctags: + * - [x] constant + * - [x] define + * - [ ] event + * - [x] function + * - [ ] module + * - [ ] net + * - [ ] port + * - [x] register + * - [x] task + * - [ ] block + * - [ ] instance + * - [x] class + * - [x] enum + * - [x] interface + * - [x] modport + * - [x] package + * - [ ] program + * - [x] prototype + * - [x] struct + * - [x] typedef + * - [z] member + * - [x] ifclass + * - [x] nettype + */ + +package oop; + +`define MACRO 1234 // NB: Shouldn't the ctag for this be outside of the package? (ctags bug?) + +/* Constants */ + +const int ANSWER_TO_LIFE = 42; +localparam real APPROX_PI = 3.14; + +/* Methods */ + +task display_int(int x); + $display("%0d", x); +endtask + +function automatic resolve_nettype(real driver[]); + resolve_nettype = 0.0; + foreach (driver[i]) + resolve_nettype += driver[i]; +endfunction + +/* Typedefs */ + +nettype real net_t with resolve_nettype; + +typedef struct packed { + logic [7:0] data; + logic parity; +} struct_t; + +typedef union packed { + logic [7:0] data; + logic [3:0] control; +} union_t; + +typedef enum { + red, + yellow, + green +} enum_t; + +/* Classes */ + +interface class ifclass #( + type T = logic +); + pure virtual function T get_value(); + pure virtual function void set_value(T x); +endclass : ifclass + +class a_class implements ifclass #(int); + + int value; + + virtual function int get_value(); + get_value = value; + endfunction + + virtual function void put_value(int x); + value = x; + endfunction + + task print_value(); + $display("value = %0d", value); + endtask + + function value_plus(int x); + value_plus = value + x; + endfunction + +endclass : a_class + +class other_class; + + struct packed { + byte s_a, s_b, s_c; + string s_str; + } s_member; + + union packed { + byte u_a; + int u_b; + } u_member; + + enum { ready, steady, go } e_member; + + struct_t st_member; + union_t ut_member; + enum_t et_member; + +endclass : other_class + +/*virtual*/ class vclass; // NB: ctags bug!! Declaring class as virtual inhibits detection of next element. + pure virtual function void do_something(); +endclass : vclass + +/* Interface (not related to "interface class") */ + +interface spi; + + logic sclk; + logic cs_n; + logic mosi; + logic miso; + + modport master (output sclk, cs_n, mosi, input miso); + modport slave (input sclk, cs_n, mosi, output miso); + + task enable_cs(); + cs_n <= 1'b0; + endtask + + task disable_cs(); + cs_n <= 1'b1; + endtask + +endinterface : spi + +endpackage : oop

Modified: tests/ctags/oop.sv.tags 118 lines changed, 118 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,118 @@ +ANSWER_TO_LIFE�16384�oop�0 +variable: oop :: ANSWER_TO_LIFE +APPROX_PI�8�oop�0 +field: oop :: APPROX_PI +MACRO�65536�oop�0 +macro: oop :: MACRO +T�8�oop.ifclass�0 +field: oop.ifclass :: T +a_class�1�oop�0 +class: oop :: a_class +control�64�oop.union_t�0 +member: oop.union_t :: control +cs_n�16384�oop.spi�0 +variable: oop.spi :: cs_n +data�64�oop.struct_t�0 +member: oop.struct_t :: data +data�64�oop.union_t�0 +member: oop.union_t :: data +disable_cs�16�oop.spi�0 +function: oop.spi :: disable_cs +display_int�16�oop�0 +function: oop :: display_int +do_something�16�oop.vclass�0 +function: oop.vclass :: do_something +driver�32768�oop.resolve_nettype�0 +externvar: oop.resolve_nettype :: driver +e_member�2�oop.other_class�0 +enum: oop.other_class :: e_member +enable_cs�16�oop.spi�0 +function: oop.spi :: enable_cs +enum_t�4096�oop�0 +typedef: oop :: enum_t +et_member�16384�oop.other_class�0 +variable: oop.other_class :: et_member +get_value�16�oop.a_class�0 +function: oop.a_class :: get_value +get_value�16�oop.ifclass�0 +function: oop.ifclass :: get_value +go�8�oop.other_class.e_member�0 +field: oop.other_class.e_member :: go +green�8�oop.enum_t�0 +field: oop.enum_t :: green +ifclass�1�oop�0 +class: oop :: ifclass +master�8192�oop.spi�0 +union: oop.spi :: master +miso�16384�oop.spi�0 +variable: oop.spi :: miso +mosi�16384�oop.spi�0 +variable: oop.spi :: mosi +net_t�4096�oop�0 +typedef: oop :: net_t +oop�512�0 +package: oop +other_class�1�oop�0 +class: oop :: other_class +parity�64�oop.struct_t�0 +member: oop.struct_t :: parity +print_value�16�oop.a_class�0 +function: oop.a_class :: print_value +put_value�16�oop.a_class�0 +function: oop.a_class :: put_value +ready�8�oop.other_class.e_member�0 +field: oop.other_class.e_member :: ready +red�8�oop.enum_t�0 +field: oop.enum_t :: red +resolve_nettype�16�oop�0 +function: oop :: resolve_nettype +s_a�64�oop.other_class.s_member�0 +member: oop.other_class.s_member :: s_a +s_b�64�oop.other_class.s_member�0 +member: oop.other_class.s_member :: s_b +s_c�64�oop.other_class.s_member�0 +member: oop.other_class.s_member :: s_c +s_member�2048�oop.other_class�0 +struct: oop.other_class :: s_member +s_str�64�oop.other_class.s_member�0 +member: oop.other_class.s_member :: s_str +sclk�16384�oop.spi�0 +variable: oop.spi :: sclk +set_value�16�oop.ifclass�0 +function: oop.ifclass :: set_value +slave�8192�oop.spi�0 +union: oop.spi :: slave +spi�32�oop�0 +interface: oop :: spi +st_member�16384�oop.other_class�0 +variable: oop.other_class :: st_member +steady�8�oop.other_class.e_member�0 +field: oop.other_class.e_member :: steady +struct_t�4096�oop�0 +typedef: oop :: struct_t +u_a�64�oop.other_class.u_member�0 +member: oop.other_class.u_member :: u_a +u_b�64�oop.other_class.u_member�0 +member: oop.other_class.u_member :: u_b +u_member�2048�oop.other_class�0 +struct: oop.other_class :: u_member +union_t�4096�oop�0 +typedef: oop :: union_t +ut_member�16384�oop.other_class�0 +variable: oop.other_class :: ut_member +value�16384�oop.a_class�0 +variable: oop.a_class :: value +value_plus�16�oop.a_class�0 +function: oop.a_class :: value_plus +vclass�1�oop�0 +class: oop :: vclass +x�32768�oop.a_class.put_value�0 +externvar: oop.a_class.put_value :: x +x�32768�oop.a_class.value_plus�0 +externvar: oop.a_class.value_plus :: x +x�32768�oop.display_int�0 +externvar: oop.display_int :: x +x�32768�oop.ifclass.set_value�0 +externvar: oop.ifclass.set_value :: x +yellow�8�oop.enum_t�0 +field: oop.enum_t :: yellow

Modified: tests/ctags/sysverilog.sv 192 lines changed, 192 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,192 @@ +/* Tests the following SystemVerilog ctags: + * - [x] constant + * - [x] define + * - [x] event + * - [x] function + * - [x] module + * - [x] net + * - [x] port + * - [x] register + * - [x] task + * - [x] block + * - [x] instance + * - [ ] class + * - [ ] enum + * - [ ] interface + * - [ ] modport + * - [ ] package + * - [x] program + * - [ ] prototype + * - [ ] struct + * - [ ] typedef + * - [ ] member + * - [ ] ifclass + * - [ ] nettype + */ + +`timescale 1ns/1ps +`default_nettype none + +`define DEFAULT_WIDTH 32 +`define BITS_TO_BYTES(x) ((x)/8) + +module a_module #( + parameter WIDTH = `DEFAULT_WIDTH, + localparam BYTES = `BITS_TO_BYTES(WIDTH) +) ( + input clk, reset, + input logic [WIDTH-1:0] data_in, + input logic valid, + input wire [BYTES-1:0] byte_en, + output wire [WIDTH-1:0] data_out +); + + wire be_filtered [BYTES-1:0]; + + genvar i; + generate + for (i = 0; i < BYTES; i++) begin : be_filtered_gen + logic x; + and and_gate ( // NB: this SHOULD be detected as an instance (ctags bug?) + x, + byte_en[i], + valid + ); + assign be_filtered[i] = x; + end + endgenerate + + wire [BYTES-1:0][7:0] data_in_bytes; + reg [BYTES-1:0][7:0] data_out_bytes; + + assign data_in_bytes = data_in; + assign data_out = data_out_bytes; + + always @(posedge clk, posedge reset) begin : main_block + if (reset) + data_out_bytes <= '0; + else begin + int i; + for (i = 0; i < BYTES; i++) + if (be_filtered[i]) + data_out_bytes[i] <= data_in_bytes[i]; + end + end + +endmodule : a_module + +program generate_signals #( + parameter NUM_UUT = 4, + parameter UUT_WIDTH = 64, + localparam UUT_BYTES = `BITS_TO_BYTES(UUT_WIDTH) +) ( + input logic clk, reset, + output logic [UUT_WIDTH-1:0] data_in, + output logic valid_uut [NUM_UUT-1:0], + output logic [UUT_BYTES-1:0] byte_en, + output event finished // NB: counts as "port", not "event" +); + + task write_byte( + byte byte_data, + int byte_index, + int uut_index + ); + begin + logic [UUT_BYTES-1:0][7:0] data_in_bytes; + data_in_bytes = '0; + data_in_bytes[byte_index] = byte_data; + data_in = data_in_bytes; + byte_en = UUT_BYTES'(1) << byte_index; + + valid_uut[uut_index] <= 1'b1; + @(posedge clk); + valid_uut[uut_index] <= 1'b0; + end + endtask + + initial begin + @(negedge reset); + @(posedge clk); + + write_byte(8'h12, 3, 0); + write_byte(8'h34, 2, 0); + write_byte(8'h56, 1, 0); + write_byte(8'h78, 0, 0); + + @(posedge clk); + + -> finished; + end + +endprogram : generate_signals + +module testbench; + + localparam NUM_UUT = 4; + localparam UUT_WIDTH = 64; + localparam UUT_BYTES = `BITS_TO_BYTES(UUT_WIDTH); + + logic clk = 1'b0, reset = 1'b0; + logic [UUT_WIDTH-1:0] data_in; + logic valid_uut [NUM_UUT-1:0]; + logic [UUT_BYTES-1:0] byte_en; + + generate + for (genvar j = 0; j < NUM_UUT; j++) begin : uut_gen + logic [UUT_WIDTH-1:0] data_out; + a_module #( // NB: this SHOULDN'T be detected as a module declaration (ctags bug) + .WIDTH (UUT_WIDTH) + ) uut ( // but this should be detected as an instance (ctags works) + .valid (valid_uut[j]), + .* + ); + end + endgenerate + + event trigger_success, trigger_failure, finished; + + function logic compare( + logic [UUT_BYTES-1:0][7:0] A, B, + logic [UUT_BYTES-1:0] mask + ); + begin + int i; + for (i = 0; i < UUT_BYTES; i++) + if (mask[i] && (A[i] != B[i])) begin + return 1'b0; + end + compare = 1'b1; // same as return 1'b1 + end + endfunction + + always begin : clk_gen + clk = ~clk; + #0.5; + end + + initial begin : reset_gen + reset = 1'b1; + #3.5; + reset = 1'b0; + end + + generate_signals #( + .NUM_UUT (NUM_UUT), + .UUT_WIDTH (UUT_WIDTH) + ) gen_signals ( + .* + ); + + initial begin + @finished; + + if (compare(uut_gen[0].data_out, 64'h 00000000_12_34_56_78, 8'b 0000_1111)) + $display("Comparison succeeded."); + else + $display("Comparison failed!"); + + $finish; + end + +endmodule : testbench

Modified: tests/ctags/sysverilog.sv.tags 118 lines changed, 118 insertions(+), 0 deletions(-) =================================================================== @@ -0,0 +1,118 @@ +A�32768�testbench.compare�0 +externvar: testbench.compare :: A +B�32768�testbench.compare�0 +externvar: testbench.compare :: B +BITS_TO_BYTES�65536�0 +macro: BITS_TO_BYTES +BYTES�8�a_module�0 +field: a_module :: BYTES +DEFAULT_WIDTH�65536�0 +macro: DEFAULT_WIDTH +NUM_UUT�8�generate_signals�0 +field: generate_signals :: NUM_UUT +NUM_UUT�8�testbench�0 +field: testbench :: NUM_UUT +UUT_BYTES�8�generate_signals�0 +field: generate_signals :: UUT_BYTES +UUT_BYTES�8�testbench�0 +field: testbench :: UUT_BYTES +UUT_WIDTH�8�generate_signals�0 +field: generate_signals :: UUT_WIDTH +UUT_WIDTH�8�testbench�0 +field: testbench :: UUT_WIDTH +WIDTH�8�a_module�0 +field: a_module :: WIDTH +a_module�1024�0 +prototype: a_module +a_module�1024�testbench.uut_gen�0 +prototype: testbench.uut_gen :: a_module +be_filtered�16384�a_module�0 +variable: a_module :: be_filtered +be_filtered_gen�256�a_module�0 +namespace: a_module :: be_filtered_gen +byte_data�32768�generate_signals.write_byte�0 +externvar: generate_signals.write_byte :: byte_data +byte_en�16384�testbench�0 +variable: testbench :: byte_en +byte_en�32768�a_module�0 +externvar: a_module :: byte_en +byte_en�32768�generate_signals�0 +externvar: generate_signals :: byte_en +byte_index�32768�generate_signals.write_byte�0 +externvar: generate_signals.write_byte :: byte_index +clk�16384�testbench�0 +variable: testbench :: clk +clk�32768�a_module�0 +externvar: a_module :: clk +clk�32768�generate_signals�0 +externvar: generate_signals :: clk +clk_gen�256�testbench�0 +namespace: testbench :: clk_gen +compare�16�testbench�0 +function: testbench :: compare +data_in�16384�testbench�0 +variable: testbench :: data_in +data_in�32768�a_module�0 +externvar: a_module :: data_in +data_in�32768�generate_signals�0 +externvar: generate_signals :: data_in +data_in_bytes�16384�a_module�0 +variable: a_module :: data_in_bytes +data_in_bytes�16384�generate_signals.write_byte�0 +variable: generate_signals.write_byte :: data_in_bytes +data_out�16384�testbench.uut_gen�0 +variable: testbench.uut_gen :: data_out +data_out�32768�a_module�0 +externvar: a_module :: data_out +data_out_bytes�16384�a_module�0 +variable: a_module :: data_out_bytes +finished�16384�testbench�0 +variable: testbench :: finished +finished�32768�generate_signals�0 +externvar: generate_signals :: finished +gen_signals�4�testbench�0�generate_signals +enumerator: generate_signals testbench :: gen_signals +generate_signals�1024�0 +prototype: generate_signals +generate_signals�1024�testbench�0 +prototype: testbench :: generate_signals +i�16384�a_module�0 +variable: a_module :: i +i�16384�a_module.main_block�0 +variable: a_module.main_block :: i +i�16384�testbench.compare�0 +variable: testbench.compare :: i +main_block�256�a_module�0 +namespace: a_module :: main_block +mask�32768�testbench.compare�0 +externvar: testbench.compare :: mask +reset�16384�testbench�0 +variable: testbench :: reset +reset�32768�a_module�0 +externvar: a_module :: reset +reset�32768�generate_signals�0 +externvar: generate_signals :: reset +reset_gen�256�testbench�0 +namespace: testbench :: reset_gen +testbench�1024�0 +prototype: testbench +trigger_failure�16384�testbench�0 +variable: testbench :: trigger_failure +trigger_success�16384�testbench�0 +variable: testbench :: trigger_success +uut�4�testbench.uut_gen�0�a_module +enumerator: a_module testbench.uut_gen :: uut +uut_gen�256�testbench�0 +namespace: testbench :: uut_gen +uut_index�32768�generate_signals.write_byte�0 +externvar: generate_signals.write_byte :: uut_index +valid�32768�a_module�0 +externvar: a_module :: valid +valid_uut�16384�testbench�0 +variable: testbench :: valid_uut +valid_uut�32768�generate_signals�0 +externvar: generate_signals :: valid_uut +write_byte�16�generate_signals�0 +function: generate_signals :: write_byte +x�16384�a_module.be_filtered_gen�0 +variable: a_module.be_filtered_gen :: x

Modified: tests/meson.build 2 lines changed, 2 insertions(+), 0 deletions(-) =================================================================== @@ -260,6 +260,7 @@ ctags_tests = [ 'ctags/objectivec_interface.mm.tags', 'ctags/objectivec_property.mm.tags', 'ctags/objectivec_protocol.mm.tags', + 'ctags/oop.sv.tags', 'ctags/Package.pm.tags', 'ctags/php5_5_class_kw.php.tags', 'ctags/parenthesis-rvalue.js.tags', @@ -338,6 +339,7 @@ ctags_tests = [ 'ctags/strings.php.tags', 'ctags/strings.rb.tags', 'ctags/structure.f.tags', + 'ctags/sysverilog.sv.tags', 'ctags/tabindent.py.tags', 'ctags/test.erl.tags', 'ctags/test.go.tags',

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