[Github-comments] [geany/geany] Create filetypes.SystemVerilog.conf (#1831)

[Juzujka]

Syntaxes of SystemVerilog and Verilog are differ.
Here is list of differences:
http://systemverilogtutorial.blogspot.ru/2013/03/systemverilog-keywords.html
I've add keywords from this list.
It is incorrect to apply SystemVerilog syntax to Verilog code.

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