<p>Syntaxes of SystemVerilog and Verilog are differ.<br>
Here is list of differences:<br>
<a href="http://systemverilogtutorial.blogspot.ru/2013/03/systemverilog-keywords.html" rel="nofollow">http://systemverilogtutorial.blogspot.ru/2013/03/systemverilog-keywords.html</a><br>
I've add keywords from this list.<br>
It is incorrect to apply SystemVerilog syntax to Verilog code.</p>

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