[Github-comments] [geany] Variables list does not parse Verilog 2001 style module port declarations properly (#670)

[Colomban Wendling]

But don't rush to it and see how it is in [Universal CTags](https://github.com/universal-ctags/ctags/blob/master/parsers/verilog.c), there were many changes to the Verilog parser so we might simply need to update our copy.

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https://github.com/geany/geany/issues/670#issuecomment-143545929
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