[Github-comments] [geany] Variables list does not parse Verilog 2001 style module port declarations properly (#670)

[pcsanza]

Ok - I read through the Verilog parser in tagmanager/ctags/verilog.c and I see (mostly) how it works - and more importantly how it does not work for my specific case.  I think I even see an additional case where I suspect it may not work (dealing with multi dimensional arrays, which was also a feature added in the 2001 language update)

I think the next step for me is to look at the Universal CTags for Verilog and see if it would would already address my issues. 

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https://github.com/geany/geany/issues/670#issuecomment-143567313
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