[Geany-devel] Using Geany for VHDL / Verilog

[Kelvin Gardiner]

Hi,

I've been looking at Geany for editing VHDL / Verilog files. Overall it 
works well with the exception of picking up symbols in the code.  VHDL 
variables are recognizing (is this a because variable var_name is used 
for another language?) but signals are not.

How does Geany recognize symbols, I can't find any config files (I may 
of missed them) so presumably it is done in the code. How hard would it 
be to add symbol recognition for VHDL / Verilog. If it is reasonably 
straight forward I don't mind try to do this.

Regards,
Kelvin Gardiner