I'm a keyboard user with carpal tunnel. When I search for a string, half the time it's going to be above the cursor in the file. Unfortunately, the default option in the Question dialog is "Cancel":
![image](https://cloud.githubusercontent.com/assets/33569/17943220/5321d8d0-69ef-11e6-9866-b6c0408cda2c.png)
I think a more useful default would be to Find again. If I want to Cancel, I'll press Esc. If I want to find again, I have to press two keystrokes (Alt+F, or Right Arrow then Enter). I know …
[View More]one extra keystroke is not much, but they add up.
Any thoughts on making `Find` the default?
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https://github.com/geany/geany/issues/1192
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For a verilog file, the variables list parses the old (1995) style verilog module declarations. Verilog 2001 enhanced the syntax and seems to confuse Geany....
1995 syntax:
module (foo, bar, buz);
input foo; // foo port
output bar; // bar port
output buz; // buz port
reg buz; // buz variable
2001 syntax:
module (
input wire foo, // foo port is a wire
output wire bar, // bar port is a wire
output reg buz // buz port is a variable
);
// note: the "wire" is optional and the ports could have …
[View More]been declared with or without
Geany variables list seems to get confused by the 2001 style. It seems to parse the wire keyword as the variable name if I keep the optional "wire" keyword:
![image](https://cloud.githubusercontent.com/assets/14856598/10121213/521dc426-64af-11e5-8c40-bc47d504da8d.png)
If I omit the "wire" keyword, Geany still gets confused, but in a different way. It seems to parse every other variable and then parse the "input" or "output" keywords as variables in some cases:
![image](https://cloud.githubusercontent.com/assets/14856598/10121233/11c50b7c-64b0-11e5-9680-b3421e7c5bea.png)
If someone who knows the code base can even point me to the module(s) doing the parsing for the variables, I may be able to help create the fix/enhancement for this. I'd be happy to try anyway. I am not familiar with the Geany code base so just getting started seems like an insurmountable task.
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SystemVerilog is almost identical syntax to Verilog. It could be quite easy to support SystemVerilog filetype (.sv) using same rules as Verilog which is already implemented.
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I am looking for some kind of "Console View" like it is available for example in Eclipse.
Currently a terminal / shell opens when executing a script in Geany. In this shell one can see the process streams stdout and stderr and can write to stdin of the new process.
However, I would rather eliminate this new terminal window popping up and changing focus each time I launch a script in Geany.
I think it is better to have the process communication (stdout, stdin, stderr) embedded in a view within …
[View More]Geany like it is done in many IDEs. The different streams could be colored e.g. stderr in red and stdin (input from the user) in green.
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https://github.com/geany/geany/issues/675
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Hello!
Can Dart be supported in geany
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Reply to this email directly or view it on GitHub:
https://github.com/geany/geany/issues/3313
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