[Github-comments] [geany/geany] Variables list does not parse Verilog 2001 style module port declarations properly (#670)

[pcsanza]

This is related to #1162.  Once the Verilog parser from u-ctags is merged, this issue will most likely be addressed. I looked at this a while back and determined that the u-ctags parser already appears to address the newer Verilog syntax properly.

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