[Github-comments] [geany] Variables list does not parse Verilog 2001 style module port declarations properly (#670)

[pcsanza]

Ok - took me a while.  I did look at Universal CTags and it appears that it already addresses the Verilog 2001 syntax (including both Verilog and Structured Verilog).  So what are the next steps and how can I help?

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Reply to this email directly or view it on GitHub:
https://github.com/geany/geany/issues/670#issuecomment-144724358
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