[Geany-Devel] Which path should I take regarding (System)Verilog tag parser?
ivzeivze at xxxxx
Mon Mar 2 08:51:29 UTC 2020
How to develop an opensource project?
1) Hack the project yourself.
2) Find out that someone did it before you.
4) Curse yourself you didn't do point 2 before point 1 =))))
So I've learned, that the copy of ctags (at least regarding the verilog parser) is an old snapshot
of what has been developed into
The parser there has been rewritten to properly support both SystemVerilog and classic Verilog in separate and to do hierarchical tagging.
So now I have a question to answer for myself, should I (with prospects for future merge into mainstream geany):
1) Try to backport that parser into geany.
2) Keep my simplified rewritten version, that works and is a descendant of the classic ctags verilog.c parser.
3) Wait until someone merges current ctags into geany, thus bringing the desired (System)Verilog update together with many other.
Waiting for an advice!
Best regards, Ivan Zelinskiy (aka ivzeivze)
More information about the Devel