[Geany-Devel] Self-introduction =)

[ivze]

Good day!

My name is Ivan Zelinskiy.

Who am I?

First of all I am a practicing FPGA developer writing my code in Verilog 
and SystemVerilog. I also know C/C++.

Secondary I am a geany user, as it's my favorite editor in Linux - the 
OS (of choice!) of my workstation.

As a result of the former two statements, I support my own branch of 
patched geany, gradually fixing issues, "paper-cuts", extending language 
support beyond the mainstream features.


It was a steady gradual process, the first commit of my branch dates 
back to 2015.  It all started with fixing "localparam" keyword, that 
would not highlight properly in /data/filedefs/filetypes.verilog. It all 
ended in rewriting a good part of /ctags/parsers/verilog.c to fix tag 
generation to include some SystemVerilog features and implement a better 
support for classical Verilog constructs, that would otherwise often 
produce "haywire" results while being parsed.

The complete list of changes is to be created =).

My branch of geany is published on github: https://github.com/ivzeivze/geany

It's a diff-patched geany/master, that is back-merged to my local 
historical branch, kept out of public sight (it's messy! =)) I am 
currently testing the changes, introduced by exporting, by means of 
everyday use. But it seems pretty stable.

I would be glad to see my work merged back into mainstream geany. Yet 
likely some clean up should be done before issuing a pull request.


With best regards to devel subscribers,

Ivan Zelinskiy.