[Geany-devel] Using Geany for VHDL / Verilog

Nick Treleaven nick.treleaven at xxxxx
Thu Nov 26 12:36:17 UTC 2009

On Thu, 26 Nov 2009 11:03:31 +0000
Kelvin Gardiner <kelvin at mbmn.net> wrote:

> I've fixed the VHDL symbols, two patches are attached for src/symbols.c 
> and tagmanager/vhdl.c.

Thanks, applied.

> I tried creating a tags file for auto-completing functions in standard 
> IEEE VHDL packages (similar to having gtk tags). I've done this by 
> adding vhdl.tags in to /usr/share/geany but this doesn't work. I copied 
> c99.tags to vhdl.tags and that didn't work either so presumably I need 
> to add something else somewhere to get this working. What do I need to do?

Check the manual - it should be called something like std.vhdl.tags and
placed in /usr/share/geany/tags or ~/.config/geany/tags.

> I'd like to create symbols for Verilog as well. If I copy vhdl.c and 
> change it as needed and modify the symbols.c to pickup Verilog files. 
> Will these symbols get picked up or do I need to get geany to recognise 
> Verilog files. Also, how to get geany to do syntax highlighting for Verilog.

It sounds like you want a new filetype for Verilog as it seems this is
quite different from VHDL. See the HACKING file for how to add a
filetype. There is a Verilog tag parser in the ctags project you could
adapt and a lexer for highlighting in the Scintilla project src


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