[Geany-devel] Using Geany for VHDL / Verilog

[Kelvin Gardiner]

Hi,

I've fixed the VHDL symbols, two patches are attached for src/symbols.c 
and tagmanager/vhdl.c.

The changes are:

Added support of Alias symbol in symbols.c
Renamed / added symbols groups and added icons for displayed groups in 
symbols.c
Correct symbol types in vhdl.c

In some cases several symbols are in the same group. For example VHDL 
variables, signals and constants are similar to  variables in other 
programming languages, so all this types are grouped as variables. I've 
done this to avoid introducing VHDL specific symbol types.


I tried creating a tags file for auto-completing functions in standard 
IEEE VHDL packages (similar to having gtk tags). I've done this by 
adding vhdl.tags in to /usr/share/geany but this doesn't work. I copied 
c99.tags to vhdl.tags and that didn't work either so presumably I need 
to add something else somewhere to get this working. What do I need to do?


I'd like to create symbols for Verilog as well. If I copy vhdl.c and 
change it as needed and modify the symbols.c to pickup Verilog files. 
Will these symbols get picked up or do I need to get geany to recognise 
Verilog files. Also, how to get geany to do syntax highlighting for Verilog.

Regards,
Kelvin




Kelvin Gardiner wrote:
> Hi,
>
> Thanks for the patch. I've just had chance to give it a try. I'll have 
> a look at fixing the other VHDL tags, and send a patch when done.
>
> Regards,
> Kelvin
>
> Nick Treleaven wrote:
>> On Fri, 20 Nov 2009 13:41:17 +0000
>> Kelvin Gardiner <kelvin at mbmn.net> wrote:
>>
>>  
>>> I've attached a simple counter testbench. I've compiled the current 
>>> code     
>>
>> Thanks.
>>
>>  
>>> from svn and get the same issue. The only other tag listed in the 
>>> VHDL tag file that works is function. Is the correct set of tags 
>>> been called?
>>>     
>>
>> I made a small change to get signals in the symbol list. You might like
>> to look at the commit and the HACKING file and make a patch to get
>> other tag types shown for VHDL:
>>
>> http://geany.svn.sourceforge.net/viewvc/geany?view=rev&revision=4446
>>
>> Also, it's worth saying that the CTags VHDL parser has been updated
>> quite a bit but this has made it 3 times bigger. Not sure whether we
>> want to upgrade to that.
>>
>>  
>>> Nick Treleaven wrote:
>>>    
>>>> On Fri, 20 Nov 2009 11:45:16 +0000
>>>> Kelvin Gardiner <kelvin at mbmn.net> wrote:
>>>>
>>>>        
>>>>> What I meant by symbols was the symbols tab at the the right-hand 
>>>>> side of the window.  When editing a C file this list functions, 
>>>>> variables etc. I'd like similar functionality for VHDL and Verilog.
>>>>>             
>>>> If you provide a sample file I can try to improve the symbols parsed.
>>>>
>>>> I think probably the problem is the tagmanager/vhdl.c parser hasn't
>>>> been updated to work with tagmanager tag types (VhdlKinds).
>>>>
>>>>       
>>
>> Regards,
>> Nick
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>>   
>
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