[Geany-devel] Using Geany for VHDL / Verilog
nick.treleaven at xxxxx
Tue Nov 24 16:29:11 UTC 2009
On Fri, 20 Nov 2009 13:41:17 +0000
Kelvin Gardiner <kelvin at mbmn.net> wrote:
> I've attached a simple counter testbench. I've compiled the current code
> from svn and get the same issue. The only other tag listed in the VHDL
> tag file that works is function. Is the correct set of tags been called?
I made a small change to get signals in the symbol list. You might like
to look at the commit and the HACKING file and make a patch to get
other tag types shown for VHDL:
Also, it's worth saying that the CTags VHDL parser has been updated
quite a bit but this has made it 3 times bigger. Not sure whether we
want to upgrade to that.
> Nick Treleaven wrote:
> > On Fri, 20 Nov 2009 11:45:16 +0000
> > Kelvin Gardiner <kelvin at mbmn.net> wrote:
> >> What I meant by symbols was the symbols tab at the the right-hand side
> >> of the window. When editing a C file this list functions, variables
> >> etc. I'd like similar functionality for VHDL and Verilog.
> > If you provide a sample file I can try to improve the symbols parsed.
> > I think probably the problem is the tagmanager/vhdl.c parser hasn't
> > been updated to work with tagmanager tag types (VhdlKinds).
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