[Geany-devel] Using Geany for VHDL / Verilog
nick.treleaven at xxxxx
Fri Nov 20 12:28:34 UTC 2009
On Fri, 20 Nov 2009 11:45:16 +0000
Kelvin Gardiner <kelvin at mbmn.net> wrote:
> What I meant by symbols was the symbols tab at the the right-hand side
> of the window. When editing a C file this list functions, variables
> etc. I'd like similar functionality for VHDL and Verilog.
If you provide a sample file I can try to improve the symbols parsed.
I think probably the problem is the tagmanager/vhdl.c parser hasn't
been updated to work with tagmanager tag types (VhdlKinds).
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