[Geany-devel] Using Geany for VHDL / Verilog

[Nick Treleaven]

On Mon, 7 Dec 2009 17:57:18 +0000
Nick Treleaven <nick.treleaven at btinternet.com> wrote:

> > I've attached a number of patches and new files to add Verilog syntax 
> > highlighting and symbols. I've taken the Verilog lexer directly from 
> > Scintilla.
> 
> Thanks for the patch & sorry for the slow response. It's now applied in
> SVN, with some changes:

Also just committed:
Fix using common style colours for Verilog.

We like the default style colours to be reasonably consistent across
filetypes.

Regards,
Nick