[Geany-devel] Using Geany for VHDL / Verilog
nick.treleaven at xxxxx
Mon Dec 7 17:57:18 UTC 2009
On Fri, 27 Nov 2009 20:02:45 +0000
Kelvin Gardiner <kelvin at mbmn.net> wrote:
> I've attached a number of patches and new files to add Verilog syntax
> highlighting and symbols. I've taken the Verilog lexer directly from
Thanks for the patch & sorry for the slow response. It's now applied in
SVN, with some changes:
Adjusted some styleset_verilog_init allocations that were too big.
Removed the commented VHDL symbols.c lines (not sure what they were
Added a get.h include to verilog.c to fix build.
BTW You might like to use the 'svn diff >patch.diff' command another
time as it's probably easier than diffing each file manually ;-)
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