[geany/geany] e0ef85: Verilog: Fix parsing initializers

[Colomban Wendling]

Branch:      refs/heads/master
Author:      Colomban Wendling <ban at herbesfolles.org>
Committer:   Colomban Wendling <ban at herbesfolles.org>
Date:        Fri, 19 Jul 2013 15:17:55 UTC
Commit:      e0ef859c7fd77215a4cde375fc96ab37731e97e1
             https://github.com/geany/geany/commit/e0ef859c7fd77215a4cde375fc96ab37731e97e1

Log Message:
-----------
Verilog: Fix parsing initializers

Import upstream CTags fix for parsing Verilog initalizers
(fixes parsing of test bug2747828.v).


Modified Paths:
--------------
    tagmanager/ctags/verilog.c
    tests/ctags/bug2747828.v.tags

Modified: tagmanager/ctags/verilog.c
1 files changed, 1 insertions(+), 0 deletions(-)
===================================================================
@@ -229,6 +229,7 @@ static void tagNameList (const verilogKind kind, int c)
 		c = skipWhite (c);
 		if (c == '=')
 		{
+			c = skipWhite (vGetc ());
 			if (c == '{')
 				skipPastMatch ("{}");
 			else


Modified: tests/ctags/bug2747828.v.tags
1 files changed, 0 insertions(+), 1 deletions(-)
===================================================================
@@ -1,3 +1,2 @@
 # format=tagmanager
-9�16384�0
 ramaddr_0�16384�0



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