You can view, comment on, or merge this pull request online at:
https://github.com/geany/geany/pull/1852
-- Commit Summary --
* Added syntax highlighting keywords for Verilog-2001 "generate" statements and localparams
-- File Changes --
M data/filedefs/filetypes.verilog (4)
-- Patch Links --
https://github.com/geany/geany/pull/1852.patch https://github.com/geany/geany/pull/1852.diff
Built from scratch, tested syntax highlighting which works well. Attached a snapshot displaying syntax highlighting in a generate block.
@seanboree did you check all the words added are valid and correct?
@azonenberg its traditional to keep the word list sorted so it is easy to check for omissions
@elextr Yes.
@azonenberg pushed 1 commit.
acd1175 Alphabetically sorted keywords in filetypes.verilog
@elextr The existing list wasn't sorted so I didn't know. Fixed.
@azonenberg pushed 2 commits.
c2243d3 Merge branch 'master' of git://github.com/geany/geany 5396354 Added support for syntax-highlighting BSDL files as VHDL
Closed #1852.
Superseded by https://github.com/geany/geany/pull/4037.
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