SystemVerilog syntax highlighting You can view, comment on, or merge this pull request online at:
https://github.com/geany/geany/pull/1831
-- Commit Summary --
* Create filetypes.SystemVerilog.conf
-- File Changes --
A data/filedefs/filetypes.SystemVerilog.conf (65)
-- Patch Links --
https://github.com/geany/geany/pull/1831.patch https://github.com/geany/geany/pull/1831.diff
If all you want is to treat .sv extension as verilog, just add it to your filetype.extensions under verilog=
Syntaxes of SystemVerilog and Verilog are differ. Here is list of differences: http://systemverilogtutorial.blogspot.ru/2013/03/systemverilog-keywords.html I've add keywords from this list. It is incorrect to apply SystemVerilog syntax to Verilog code.
Closed #1831.
Superseded by https://github.com/geany/geany/pull/4039.
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