Reply to this email directly, view it on GitHub, or unsubscribe.
You are receiving this because you are subscribed to this thread.
For the sake of "keeping the things the way they were", I've gone with option 1, and tried my best at grouping the keywords into things that are used for declaring signals/constants, and things that are not. I think the result is good.
I have also decided to add all the standard system functions/tasks.
This is how it looks now (with word3 highlighted in a lighter blue). Signal declarations use keywords of one type, other control structures use the other. I think it looks nice.
geany_verilog_keywords.png (view on web)
I've pushed the new version to this PR (and rebased it on top of master, while I was at it).
—
Reply to this email directly, view it on GitHub, or unsubscribe.
You are receiving this because you are subscribed to this thread.