@techee: there's only one issue pending which is whether it is OK to leave the comments I put in group_SYSVERILOG or if I should remove those as well.

These can stay.

I also re-generated the ctags unit tests for Verilog and added two for SystemVerilog.

There's one thing I noticed - I think you should also add mappings for types that can appear as parents of other symbols. For instance, because of the missing oop package mapping, the symbol tree doesn't generate it in the hierarchy and the bottom part of the screenshot below shows just flat symbol list instead of a proper tree.
Screenshot.2024-11-20.at.0.18.08.png (view on web)

While doing so, I noticed a couple of issues/bugs in ctags (I think), but those should be fixed in ctags.

If you decide to update the ctags parsers, you should get it merged to ctags first and then open a PR in Geany with the change.

Apart from the symbol tree issue, the PR looks pretty good to me 👍.

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