Fixes #4072 (re: my_module inst (d, q); creating tags for both the instance inst and the module my_module).
The unit tests have been updated accordingly.

Also includes a minor amendment to #4039 to fix the tag grouping for SystemVerilog so that enum objects are put in the same group as struct/union objects, which makes more sense than putting them in the same group as typedefs (which are types, not objects).

You can view, comment on, or merge this pull request online at:

https://github.com/geany/geany/pull/4075

Commit Summary

dd9f515 Change icon of SystemVerilog struct/enum objects
a7ae4b5 tagmanager: Verilog: don't tag module of instances

File Changes

(3 files)

M src/tagmanager/tm_parser.c (7)
M tests/ctags/sysverilog.sv (4)
M tests/ctags/sysverilog.sv.tags (4)

Patch Links:

https://github.com/geany/geany/pull/4075.patch
https://github.com/geany/geany/pull/4075.diff

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