For a verilog file, the variables list parses the old (1995) style verilog module declarations. Verilog 2001 enhanced the syntax and seems to confuse Geany....

1995 syntax:

module (foo, bar, buz);
input foo; // foo port
output bar; // bar port
output buz; // buz port
reg buz; // buz variable

2001 syntax:

module (
input wire foo, // foo port is a wire
output wire bar, // bar port is a wire
output reg buz // buz port is a variable
);

// note: the "wire" is optional and the ports could have been declared with or without

Geany variables list seems to get confused by the 2001 style. It seems to parse the wire keyword as the variable name if I keep the optional "wire" keyword:

If I omit the "wire" keyword, Geany still gets confused, but in a different way. It seems to parse every other variable and then parse the "input" or "output" keywords as variables in some cases:

If someone who knows the code base can even point me to the module(s) doing the parsing for the variables, I may be able to help create the fix/enhancement for this. I'd be happy to try anyway. I am not familiar with the Geany code base so just getting started seems like an insurmountable task.

—
Reply to this email directly or view it on GitHub.