I don't know what's the policy on file extensions in this project; is it OK to add file extensions even if they're not exactly the same file type?
To emphasise, adding an extension tells Geany to treat `*.sv` files as Verilog, not that Geany supports SystemVerilog.
Probably better would be to add a custom filetype (rt"fine"m) that adds the keywords and assign `*.sv` to that. But as @cousteaulecommandant says the parser behaviour is not configurable, and possibly lexer subtleties may be wrong too. Custom filetypes are a "best effort" thing.
A proper solution would be to actually implement a proper SystemVerilog parser in Geany (extending the one for Verilog)
That would be even better, so [your wish is my command :grin:](https://github.com/geany/geany/blob/3787677de43204d1396c8f5439e82e90fe61b8a4...)
So now all "somebody" has to do is make a built-in Geany filetype using that, see how the Verilog filetype is done, read HACKING and for example look at recent new filetypes such as [Julia](https://github.com/geany/geany/pull/2584)