Reply to this email directly, view it on GitHub, or unsubscribe.
You are receiving this because you are subscribed to this thread.
I don't know how much finished this PR is but I added a few comments.
Getting there, slowly but surely. Thanks a lot for your feedback and guidance :)
I'm not sure if you want to apply some of the changes you made to #4037 to this PR as well.
Yeah, as soon as I did that keyword rearrangement there I knew I would regret it 😩 It needs to be done here as well for consistency, problem is that there are many more keywords here and with all the OOP in SystemVerilog the barrier between "type" and "not type" gets fuzzier. But I'll figure it out.
Finally, a unit test should be added under tests/ctags (check the HACKING file for more details). The unit test should include some SystemVerilog code that covers all the kinds except those mapped to
tm_tag_undef_t.
Noted! I'll see what I can make up.
—
Reply to this email directly, view it on GitHub, or unsubscribe.
You are receiving this because you are subscribed to this thread.